Using The Dbb Signal - IBM PowerPC 604 User Manual

• If an ARTRY assertion occurs the same cycle as its corresponding DBG, the
ARTRY will disqualify the data bus grant in that cycle and the 604 will not initiate
any data transaction on the following cycle regardless of whether any other data
transactions are queued However, on the following cycle (the cycle after the
ARTRY assertion) the 604 processor will respond to a qualified data bus grant if it
has previously queued data transactions. Figure 8-9 shows an example where a write
address tenure receives an ARTRY snoop response in the same cycle the system
asserts DBWO and DBG (cycle 6) to grant the write data tenure before a previously
requested read data tenure. Following the ARTRY assertion, the qualified DBG
assertion to the 604 in cycle 7 will be accepted for the read data tenure.
2 3
4
s
I
6
I
7
8 9 10
System Clock
TS
~
;!;RTRV
Master 1
'DBtl
~
Qualified~
I I
ARTRY,
kills
_1
QDBG for WRITE" I I
I I I I
I I I
Internal Data
u
Bus Request
:
\...._._--"'-: -~:
tmB
'-----'----'---_.;..-----'----..:.,._--~1----.:.......1
I I I
: : \ for ¥EAD
¥ ¥
Figure 8-9. Quallfled DBG Generation Following ARTRY
8.4.1.2 Using the DBB Signal
The DBB signal should be connected between masters if data tenure scheduling is left to
the masters. Optionally, the memory system can control data tenure scheduling directly
with DBG. However, it is possible to ignore the DBB signal in the system if the DBB input
is not used as the final data bus allocation control between data bus masters, and if the
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PowerPC 604 RISC Microprocessor User's Manual