Transfer Error Acknowledge; System Interrupt, Checkstop, And Reset Signals - IBM PowerPC 604 User Manual

Timing Comments Assertion-Must occur during the bus clock cycle immediately after
TA is asserted if a retry is required. The DRTRY signal may be held
asserted for multiple bus clock cycles. When DRTRY is negated,
data must have been valid on the previous clock with TA asserted.
Negation-Must occur during the bus clock cycle after a valid data
beat. This may occur several cycles after DBB is negated, effectively
extending the data bus tenure.
Startup-DRTRY is sampled at the negation of HRESET; if DRTRY
is asserted, fast-L2 mode is selected. If DRTRY is negated at startup,
DRTRY is enabled. DRTRY must be negated during normal
operation (following HRESET) if fast-L2/data streaming mode is
selected. ·
7 .2.8.3 Transfer Error Acknowledge (TEA)-lnput
The transfer error acknowledge (TEA) signal is input only on the 604. Following are the
state meaning and timing comments for the TEA signal.
State
Meaning Asserted-Indicates that a bus error occurred. Causes a machine
check exception (and possibly causes the processor
to
enter
checkstop state if machine check enable bit is cleared
(MSR[ME] = 0)). For more information, see Section 4.5.2.2,
"Checkstop State (MSR[ME]
=
0)." Assertion terminates the current
transaction; that is, assertion of TA and DRTRY are ignored. The
assertion of TEA causes the negation/high impedance ofDBB in the
next clock cycle. However, data entering the GPR or the cache are
not invalidated. Note that the architecture specification refers to all
exceptions as interrupts.
Negated-Indicates that no bus error was detected.
Timing Comments Assertion-May be asserted while DBB is asserted, or during valid
DRTRY window. In fast-L2/data streaming mode, the 604 will not
recognize TEA the cycle after TA during a read operation due to the
absence of a DRTRY assertion opportunity. The TEA signal should
be asserted for one cycle only.
Negation- The TEA signal must be negated no later than the
negation of DBB or the last DRTRY. The 604 deasserts DBB within
one bus clock cycle following the assertion of TEA.
7 .2.9 System Interrupt, Checkstop, and Reset Signals
Most of the system interrupt, checkstop, and reset signals are input signals that indicate
when exceptions are received, when checkstop conditions have occurred, and when the 604
must be reset. The 604 generates the output signal, CKSTP _OUT, when it detects a
checkstop condition. For a detailed description of these signals, see Section 8.8, "Interrupt,
Checkstop, and Reset Signals."
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PowerPC 604 RISC Microprocessor User's Manual