IBM PowerPC 604 User Manual page 232

These stages are shown in Figure 6-3. Some instructions occupy multiple stages
simultaneously and some individual execution units, such as the FPU and MCIU, have
multiple execution stages.
Fetch (IF)
-----------------,
Execute Stage
1
I
I
~---=-~ ..---~--. ~--~ ~--~ ~-~~ ~.....;::m~~ I
I
~-""""""""- ~-~- '--~---' ~-~- ~--- ~-=---
I
Write-Back (W)
I
I
I
_______________ .J
Figure 6-3. Plpellne Diagram
Pipelines for typical instructions for each of the execution units are shown in Figure 64.
Note that this figure does not accurately reflect the latencies for all instructions that pass
through each of the pipelines. The division of instructions into branch, integer, load/store,
and ftoating-poirit instructions indicates the execution unit in which
the
instructions
execute. For example, mtspr instructions, which are not thought of as integer instructions
from a functional perspective, are considered with integer instructions here because they
execute in the MCIU.
Note that in many circumstances, complete and write-back can occur in the same cycle.
Also, integer multiply, integer divide, move to/from SPR, store, and load instructions that
miss in the cache can occupy both the final stage of execute (finish) and complete
(and
write-back) simultaneously. ·
6-6
PowerPC 604 RISC Microproceeeor Ueer'e Manual