Branch And Flow Control Instructions - IBM PowerPC 604 User Manual

Table 2-28 shows the conversions made when performing a Store Floating-Point Double
instruction. Most entries in the table indicate that the floating-point value is simply stored.
Only in a few cases are any other actions taken.
Table 2·28. Store Floating-Point Double Behavior
FPR Precision Data Type Action
Single
Nonnalized Store
Single Denormalized
Nonnalize and Store
Single
Zero
Store
Infinity
QNaN
Single SNaN Store
Double Normalized Store
Double Denormalized Store
Double Zero Store
Infinity
QNaN
Double SNaN Store
Architecturally, all floating-point numbers are represented in double-precision format
within the 604. Execution of a store floating-point single (stfs, stfsu, stfsx, stfsux)
instruction requires conversion from double- to single-precision format. If the exponent is
not greater than 896, this conversion requires denormalization. The 604 supports this
denormalization by shifting the mantissa one bit at a time. Anywhere from 1 to 23 clock
cycles are required to complete the denormalization, depending upon the value to be stored.
Because of how floating-point numbers are implemented in the 604, there is also a case
when execution of a store floating-point double (stfd, stfdu, stfdx, stfdux) instruction can
require internal shifting of the mantissa. This case occurs when the operand of a store
floating-point double instruction is a denormalized single-precision value. The value could
be the result of a load floating-point single instruction, a single-precision arithmetic
instruction, or a floating round
to
single-precision instruction. In these cases, shifting the
mantissa takes from 1 to 23 clock cycles, depending upon the value to be stored. These
cycles are incurred during the store.
2.3.4.4 Branch and Flow Control Instructions
Some branch instructions can redirect instruction execution conditionally based on the
value of bits in the CR. When the processor encounters one of these instructions, it scans
the execution pipelines to determine whether an instruction in progress may affect the
particular CR bit. If no interlock is found, the branch can be resolved immediately by
checking the bit in the CR and taking the action defined for the branch instruction.
Chapter 2. PowerPC 604 Processor Programming Model
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