Pipeline Structures - IBM PowerPC 604 User Manual

Figure 6-2. GPR Reservation Stations and Result Buses
Although it is not shown in Figure 6-1, the LSU and FPU are pipelined.
The 604's completion buffer can retire four instructions every clock cycle. In general,
instruction processing is accomplished in six stages-fetch stage, decode stage, dispatch
stage, execute stage, completion stage, and write-back stage. The instruction fetch stage
includes the clock cycles necessary to request instructions from the on-chip cache as well
as the time it takes the on-chip cache to respond
to
that request. The decode stage consists
of the time it takes to fully decode the instruction. In the complete stage, as many as four
instructions per cycle are completed in program order. In the write-back stage, results are
returned to the register file. Instructions are fetched and executed concurrently with the
execution and write-back of previous instructions producing an overlap period between
instructions. The details of these operations are explained in the following paragraphs.
6.2.1 Pipeline Structures
The master instruction pipeline of the 604 has six stages. Instructions executed by the
machine flow through these stages. Some instructions combine the completion and write-
back stages into a single cycle. Some instructions (load, store, and floating-point
instructions) flow through additional execution pipeline stages.
The six basic stages of the master instruction pipeline are as follows:
• Fetch (IF)
• Decode (ID)
• Dispatch (DS)
• Execute (E)
• Completion (C)
• Write-back (W)
Chapter 6. Instruction Timing 6-5