IBM PowerPC 604 User Manual page 364

Note that although the 604 can pipeline any write transaction behind the read transaction,
special care should be used when using the enveloped write feature. It is envisioned that
most system implementations will not need this capability; for these applications DBWO
should remain negated. In systems where this capability is needed, DBWO should be
asserted under the following scenario:
1. The 604 initiates a read transaction (either single-beat or burst) by completing the
read address tenure with no address retry.
2. Then, the 604 initiates a write transaction by completing the write address tenure,
with no address retry.
3. At this point, if DBWO is asserted with a qualified data bus grant to the 604, the 604
asserts DBB and drives the write data onto the data bus, out of order with
res~o
the address pipeline. The write transaction concludes with the 604 negating DBB.
4. The next qualified data bus grant signals the 604 to complete the outstanding read
transaction by latching the data on the bus. This assertion of DBG should not be
accompanied by an asserted DBWO.
Any number of bus transactions by other bus masters can be attempted between any of
these steps.
Note the following regarding DBWO:
• The DBWO signal can be asserted if no data bus read is pending, but it has no effect
on write ordering.
• The ordering and presence of data bus writes is determined by the writes in the write
queues at the time BG is asserted for the write address (not DBG). A cache-line
snoop push-out operation has the highest priority, and takes precedence over other
queued write operations.
• Because more than one write may be in the write queue when DBG is asserted for
the write address, more than one data bus write may be enveloped by a pending data
bus read
The arbiter must monitor bus operations and coordinate the various masters and slaves with
respect to the use of the data bus when DBWO is used. Individual DBG signals associated
with each bus device should allow the arbiter
to
synchronize both pipelined and split-
transaction bus organizations. Individual DBG and DBWO signals provide a primitive
form of source-level tagging for the granting of the data bus.
Note that use of the DBWO signal allows some operation-level tagging with respect to the
604 and the use of the data bus.
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PowerPC 604 RISC Microprocessor User's Manual