IBM PowerPC 604 User Manual page 37

1-6
- Address translation facilities for 4-Kbyte page size, variable block size, and
256-Mbyte segment size
- Separate instruction and data translation lookaside buffers (TLBs)
- Both TLBs are 128-entry and two-way set associative
- Separate IBATs and DBATs (four each) also defined as SPRs
- LRU replacement algorithm
- Hardware table search (caused by TLB misses) through hashed page tables
- 52-bit virtual address; 32-bit physical address
• Bus interface features include the following:
- Selectable processor-to-bus clock frequency ratios (1:1, 1.5:1, 2:1, and 3:1)
- A 64-bit split-transaction external data bus with burst transfers
- Support for address pipelining and limited out-of-order bus transactions
- Additional signals and signal redefinition for direct-store operations
• Multiprocessing support features include the following:
- Hardware enforced, four-state cache coherency protocol (MESI) for data cache.
Bits are provided in the instruction cache to indicate only whether a cache block
is valid or invalid
- Separate port into data cache tags for bus snooping
- Load/store with reservation instruction pair for atomic memory references,
semaphores, and other multiprocessor operations
• Power management
- Operating voltage is 3.3
±
0.3 V
- Software-initiated NAP mode suspends instruction dispatch and waits for all
activity in progress, including active and pending bus transactions, to complete.
It then shuts down
the
internal chip clocks, and enters nap mode.
• Performance monitor can be used to help in debugging system designs and
improving software efficiency, especially in multiprocessor systems.
• In-system testability and debugging features through JTAG boundary-scan
capability
PowerPC 604 RISC Microprocessor User's Manual