IBM PowerPC 604 Manuals

Manuals and User Guides for IBM PowerPC 604. We have 1 IBM PowerPC 604 manual available for free PDF download: User Manual

IBM PowerPC 604 User Manual

IBM PowerPC 604 User Manual (455 pages)

RISC

Brand: IBM | Category: Computer Hardware | Size: 40 MB

Table of Contents

Table of Contents
6
Paragraph
23
About this Book
24
Audience
25
Organization
25
Suggested Reading
26
Conventions
27
Acronyms and Abbreviations
28
Overview
32
Powerpc 604 Microprocessor Features
33
Powerpc 604 Microprocessor Hardware Implementation
38
Instruction Flow
39
Fetch Unit
39
Decode/Dispatch Unit
40
Branch Processing Unit (BPU)
40
Completion Unit
40
Rename Buffers
41
Execution Units
41
Integer Units (Ius)
41
Floating-Point Unit (FPU)
42
Load/Store Unit (LSU)
42
Memory Management Units (Mmus)
43
Cache Implementation
43
Instruction Cache
44
Data Cache
44
System Interface/Bus Interface Unit (BIU)
45
Memory Accesses
47
Signals
47
Signal Coofiguration
48
Clocking
49
Powerpc 604 Microprocessor Execution Model
50
Levels of the Powerpc Architecture
50
Registers and Programming Model
51
General-Purpose Registers (Gprs)
53
Floating-Point Registers (Fprs)
53
Condition Register (CR)
53
Floating-Point Status and Control Register (FPSCR)
54
Machine State Register (MSR)
54
Segment Registers (Srs)
54
Special-Purpose Registers (Sprs)
54
User-Level Sprs
54
Supervisor-Level Sprs
54
Instruction Set and Addressing Modes
56
Powerpc Instruction Set and Addressing Modles
56
Instruction Set
56
Calculating Effective Addresses
58
Exception Model
59
Instruction Timing
64
Power Management-Nap Mode
66
Performance Monitor
66
Powerpc 604 Processor Programming Model
67
The Powerpc 604 Processor Register Set
67
Register Set
68
604-Specific Registers
74
Instruction Address Breakpoint Register (IABR)
74
Processor Identification Register (PIR)
75
Hardware Implementation-Dependent Register 0
76
Performance Monitor Registers
77
Monitor Mode Control Register 0 (MMCRO)
77
Performance Monitor Counter Registers (Pmcl and PMC2)
79
Sampled Instruction Address Register (SIA)
81
Sampled Data Address Register (SDA)
82
Operand Conventions
82
Floating-Point Execution Models-UISA
82
Da~ Organization in Memory and Data Transfers
83
Alignment and Misaligned Accesses
83
Floating-Point Operand
83
Effect of Operand Placement on Performance
85
Instruction Set Summary
85
Classes of Instructions
87
Definition of Boundedly Undefined
87
Defined Instruction Class
87
Illegal Instruction Class
88
Reserved Instruction Class
89
Addressing Modes
89
Memory Addressing
89
Memory Operands
89
Effective Address Calculation
90
Synchronization
90
Context Synchronization
90
Execution Synchronization
91
Instruction-Related Exceptions
91
Instruction Set Overview
92
Powerpc UISA Instructions
92
Integer Instructions
92
Integer Arithmetic Instructions
92
Integer Compare Instructions
94
Integer Logical Instructions
94
Integer Rotate and Shift Instructions
95
Floating-Point Instructions
96
Floating-Point Arithmetic Instructions
96
Floating-Point Multiply-Add Instructions
97
Floating-Point Rounding and Conversion Instructions
97
Floating-Point Compare Instructions
98
Floating-Point Status and Control Register Instructions
98
Floating-Point Move Instructions
99
Load and Store Instructions
99
Self-Modifying Code
100
Integer Load and Store Address Generation
101
Register Indirect Integer Load Instructions
101
Integer Store Instructions
102
Integer Load and Store with Byte Reverse Instructions
103
Integer Load and Store Multiple Instructions
104
Integer Load and Store String Instructions
105
Floating-Point Load and Store Address Generation
106
Floating-Point Store Instructions
107
Branch and Flow Control Instructions
109
Branch Instruction Address Calculation
110
Branch Instructions
110
Condition Register Logical Instructions
111
Trap Instructions
111
Move To/From Condition Register Instructions
112
System Linkage Lnstruction-UISA
112
Move To/From Special-Purpose Register Instructions (UISA)
113
Memory Synchronization Lnstructions-UISA
113
Powerpc VEA Instructions
114
Processor Control Instructions-VEA
114
Move from Time Base Instruction
114
Memory Synchronization Instructions-VEA
115
Memory Control Instructions-VEA
116
User-Level Cache Instructions-VEA
116
User-Level Cache Instructions
117
Optional External Control Instructions
118
Powerpc OEA Instructions
118
External Control Instructions
118
System Linkage Instructions-CEA
118
Memory Control Instructions-DEA
120
Supervisor-Level Cache Management Instruction-(OEA)
120
Segment Register Manipulation Instructions
120
Translation Lookaside Buffer Management Instruction
120
Segment Register Manipulation Instructions (OEA)
121
Translation Lookaside Buffer Management Lnstructions-(OEA)
121
Recommended Simplified Mnemonics
123
Cache and Bus Interface Unit Operation
124
Data Cache Organization
126
Instruction Cache Organization
127
Mmus/Bus Interface Unit
128
Memory Coherency Actions
131
604-Initiated Load and Store Operations
131
Memory Coherency Actions on Load Operations
131
Sequential Consistency
132
Sequential Consistency Within a Single Processor
132
Weak Consistency between Multiple Processors
132
Memory Coherency Actions on Store Operations
132
Sequential Consistency Within Multiprocessor Systems
133
Memory and Cache Coherency
133
Data Cache Coherency Protocol
134
MESI State Definitions
134
Coherency and Secondary Caches
136
Page Table Control Bits
136
MESI State Diagram
136
Coherency Paradoxes in Single-Processor Systems
137
Coherency Paradoxes in Multiple-Processor Systems
138
Cacheconfiguration
138
Cache Control Instructions
139
Instruction Cache Block Invalidate (Icbi)
139
Instruction Synchronize (Isync)
140
Data Cache Block Touch (Debt) and Data Cache Block Touch for Store (Dcbtst)
140
Data Cache Block Set to Zero (Dcbz)
140
Data Cache Block Store (Dcbst)
140
Data Cache Block Flush (Dcbf)
141
Data Cache Block Invalidate (Dcbi)
141
Basic Cache Operations
141
Cache Reloads
141
Cache Cast-Out Operation
141
Cache Block Push Operation
141
Atomic Memory References
142
Snoop Response to Bus Operations
142
Cache Reaction to Specific Bus Operations
142
Enveloped High-Priority Cache Block Push Operation
145
Bus Operations Caused by Cache Control Instructions
145
Cache Control Instructions
146
Cache Actions
146
Cache Actions
149
Access to Direct-Store Segments
167
Exceptions
168
Powerpc 604 Microprocessor Exceptions
169
Exception Recognition and Priorities
172
Exception Processing
173
MSR Bit Settings
174
Enabling and Disabling Exceptions
176
Steps for Exception Processing
177
Setting MSR[RI]
177
Returning from an Exception Handler
178
Process Switching
178
Exception Definitions
179
MSR Setting Due to Exception
179
Machine Check Exception (Ox00200)
180
System Reset Exception-Register Settings
180
Machine Check Exception Enabled (MSR[ME] 1)
181
Checkstop State (MSR[ME] 0)
182
Isi Exception (Ox00400)
183
External Interrupt Exception (Ox00500)
183
Alignment Exception (Ox00600)
184
Program Exception (Ox00700)
184
Floating-Point Unavailable Exception (Ox00800)
185
Decrementer Exception (Ox00900)
186
System Call Exception (Oxoocoo)
186
Trace Exception (Oxood00)
186
Floating-Point Assist Exception (Oxooeoo)
186
Instruction Address Breakpoint Exception (Ox01300)
187
System Management Interrupt (Ox01400)
187
Power Management
188
Memory Management
190
MMU Overview
191
Memory Addressing
193
MMU Organization
193
Address Translation Mechanisms
198
Memory Protection Facilities
200
Access Protection Options for
200
General Flow of MMU Address Translation
201
Real Addressing Mode and Block Address Translation Selection
201
Page and Direct-Store Interface Address Translation Selection
203
Selection of Page Address Translation
205
Selection of Direct-Store Interface Address Translation
205
MMU Exceptions Summary
205
MMU Instructions and Register Summary
207
TLB Entry Invalidation
208
Powerpc 604 Microprocessor Instruction Summary-Control Mmus
208
Powerpc 604 Microprocessor MMU Registers
208
Real Addressing Mode
209
Block Address Translation
209
Memory Segment Model
209
Page History Recording
210
Referenced Bit
211
Changed Bit
211
Scenarios for Referenced and Changed Bit Recording
212
Page Memory Protection
213
TLB Description
213
TLB Organization
213
TLB Invalidation
215
Page Address Translation Summary
216
Page Table Search Operation
218
Page Table Updates
222
Segment Register Updates
223
Direct-Store Interface Address Translation
224
Direct-Store Interface Accesses
224
Direct-Store Segment Protection
224
Instructions Not Supported in Direct-Store Segments
225
Instructions with no Effect in Direct-Store Segments
225
Direct-Store Segment Translation Summary Flow
225
Instruction Timing
227
Instruction Timing Overview
229
Pipeline Structures
231
Description of Pipeline Stages
233
Fetch Stage
234
Decode Stage
235
Dispatch Stage
235
Execute Stage
236
Complete Stage
237
Write-Back Stage
238
MMU Overview
239
Cache Overview
239
Bus Interface Overview
241
Memory Operations
241
Write-Back Mode
241
Write-Through Mode
242
Cache-Inhibited Mode
242
Timing Considerations
243
General Instruction Flow
243
Instruction Fetch Timing
244
Cache Miss Timing Example
248
Cache Arbitration
250
Branch Prediction
250
Branch Timing Examples
251
Timing Example-Branch Timing for a BTAC Hit
251
Timing Example-Branch with BTAC Miss/Decode Correction
252
Timing Example-Branch with BTAC Miss/Dispatch Correction
254
Timing Example-Branch with BTAC Miss/Execute Correction
254
Speculative Execution
255
Instruction Dispatch and Completion Considerations
256
Rename Register Operation
257
Instruction Execution Timing
257
Execution Unit Considerations
259
Instruction Serialization
259
Dispatch Serialization Mode
260
Execution Serialization Mode
260
Postdispatch Serialization Mode
260
Serialization of String/Multiple Instructions
261
Serialization of Input/Output
261
Execution Unit Timings
261
Branch Unit Instruction Timings
261
Integer Unit Instruction Timings
261
Floating-Point Unit Instruction Timings
263
Load/Store Unit Instruction Timings
265
Isync, Rfi, and Sc Instruction Timings
267
Instruction Scheduling Guidelines
268
Instruction Dispatch Rules
268
Additional Programming Tips for the Powerpc 604 Processor
269
Instruction Latency Summary
271
Signal Descriptions
279
Signal Configuration
280
Signal Descriptions
281
Address Bus Arbitration Signals
281
Bus Request (BR)-Output
282
Address Bus Busy (ABB)
283
Address Bus Busy (ABB)-Output
283
Address Transfer Start Signals
284
Transfer Start (TS)
284
Transfer Start {TS)-Output
284
Extended Address Transfer Start (XATS)
284
Extended Address Transfer Start (XATS)-Output
284
Address Transfer Signals
285
Address Bus (AO-A31)
285
Address Bus (AO-A31}-0Utput (Memory Operations)
285
Address Bus (AO-A31)-Lnput (Memory Operations)
285
Address Bus (AO-A31}-0Utput (Direct-Store Operations)
286
Address Bus (AO-A31)-Lnput (Direct-Store Operations)
286
Address Bus Parity (APO-AP3)
286
Address Bus Parity (APO-AP3)-0Utput
286
Address Parity Error
287
Address Transfer Attribute Signals
287
Transfer Type (TTO-TT4)
288
Transfer Type
288
Transfer Size (TSIZO-TSIZ2)
289
Transfer Size {TSIZO-TSIZ2)-0Utput
290
Transfer Size
290
Transfer Burst (TBST)
291
Transfer Burst (TBST)-Output
291
Transfer Burst
291
Transfer Code (TCO-TC2)-0Utput
291
Cache Inhibit (Cl)-Output
292
Write-Through (WT)-Output
293
Global (GBL)
293
Global
293
Address Transfer Termination Signals
294
Address Acknowledge
294
Address Retry (ARTRY)
294
Address Retry (ARTRY)-Output
294
Address Retry
295
Shared (SHD)
295
Shared (SHD)-Output
295
Data Bus Arbitration Signals
296
Data Bus Grant
296
Data Bus Write Only
296
Data Bus Busy (DBB)
297
Data Bus Busy (DBB)-Output
297
Data Bus Busy
297
Data Transfer Signals
298
Data Bus (DHO-DH31, DLO-DL31)
298
Data Bus
299
Data Bus Parity (DPO--DP7)
299
Data Bus Parity (DPO-DP7)-0Utput
299
Data Bus Parity
299
Data Parity Error (DPE)-Output
300
Data Bus Disable
300
Data Transfer Termination Signals
300
Transfer Acknowledge
301
Data Retry
301
Transfer Error Acknowledge
302
System Interrupt, Checkstop, and Reset Signals
302
System Management Interrupt
303
Machine Check Interrupt
303
Reset Signals
305
Hard Reset
305
Soft Reset
305
Processor Configuration Signals
306
Timebase Enable
306
Reservation
306
L2 Intervention
306
Run
307
Halted (HALTED)
307
Cop/Scan Interface
307
Clock Signals
308
System Clock
308
Test Clock (CLK_OUT)-Output
309
Analog VDD
309
PLL Configuration
309
System Interface Operation
311
Powerpc 604 Microprocessor System Interface Overview
311
Operation of the Instruction and Data Caches
312
Operation of the System Interface
314
Direct-Store Accesses
315
Memory Access Protocol
316
Arbitration Signals
317
Address Pipelining and Split-Bus Transactions
319
Address Bus Tenure
320
Address Bus Arbitration
320
Address Transfer
322
Address Bus Parity
323
Address Transfer Attribute Signals
323
Transfer Type (TTO-TT4) Signals
323
Transfer Size (TSIZO-TSIZ2) Signals
323
Burst Ordering During Data Transfers
324
Effect of Alignment in Data Transfers
324
Alignment of External Control Instructions
326
Transfer Code (TCO-TC2) Signals
327
Address Transfer Termination
328
Data Bus Tenure
330
Data Bus Arbitration
330
Effect of ARTRY Assertion on Data Transfer and Arbitration
331
Using the DBB Signal
332
Data Bus Write Only
333
Data Transfer
333
Data Transfer Termination
334
Normal Single-Beat Termination
335
Data Transfer Termination Due to a Bus Error
338
Memory Coherency-MESI Protocol
339
Timing Examples
342
Direct-Store Operation
348
Direct-Store Transactions
350
Store Operations
351
Load Operations
351
Direct-Store Transaction Protocol Details
352
Packet 0
354
1/0 Reply Operations
354
Direct-Store Operation Timing
356
Optional Bus Configuration
358
Fast-L2/Data Streaming Mode
358
Fast-L2/Data Streaming Mode Design Considerations
359
Data Streaming in the Fast-L2/Data Streaming Mode
359
Data Valid Window in the Fast-L2/Data Streaming Mode
360
Interrupt, Checkstop, and Reset Signals
360
External Interrupts
360
Checkstops
361
Reset Inputs
361
Powerpc 604 Microprocessor Configuration During HRESET
361
Processor State Signals
362
Support for the Lwarx/Stwcx. Instruction Pair
362
IEEE 1149.1 Interface Description
362
Using Data Bus Write Only
363
Performance Monitor
365
Performance Monitor Interrupt
366
Special-Purpose Registers Used by Performance Monitor
366
Performance Monitor Counter Registers (Pmcl and PMC2)
367
PMC2 Selectable Events
369
SIA and SDA Registers
370
Sampled Instruction Address Register (SIA)
370
Sampled Data Address Register (SDA)
370
Updating SIA and SDA
370
Event Counting
372
Event Selection
373
Threshold Events
374
Threshold Conditions
374
Lateral L2 Cache Intervention
374
Warnings
375
Nonthreshold Events
375
Appendix A Powerpc Instruction Set Listings
376
Instructions Sorted by Mnemonic
376
Instructions Sorted by Opcode
384
Instructions Grouped by Functional Categories
392
Instructions Sorted by Form
402
Instruction Set Legend
413
Appendix B Invalid Instruction Forms
421
Invalid Forms Excluding Reserved Fields
421
Invalid Form with Only Bit 31 Set
425
Invalid Forms from Invalid BO Field Encodings
426
Glossary of Terms and Abbreviations
427

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