IBM PowerPC 604 User Manual page 192

• TLB invalidation-The 604 implements the optional TLB Invalidate Entry
(tlbie)
and TLB Synchronize
(tlbsync)
instructions, which can be used to invalidate TLB
entries. For more information on the
tlbie
and
tlbsync
instructions, see
Section 5.4.3.2, "TLB Invalidation."
Table 5-1 summarizes the 604 MMU features, including those defined by the PowerPC
architecture (OEA) for 32-bit processors and those specific to the 604.
Table 5-1. MMU Feature Summary
Architecturally
Feature Category Defined/ Feature
604-Speclflc
Address ranges Architecturally defined
~ 2
bytes of effective address
'l52
bytes of virtual address
t3
2
bytes of physical address
Page size Architecturally defined 4Kbytes
Segment size Architecturally defined 256Mbytes
Block address Architecturally defined Range of 128 Kbyte-256 Mbyte sizes
translation
Implemented with IBAT and DBAT registers in BAT array
Memory protection
Architecturally defined
Segments selectable as no-execute
Pages selectable as user/supervisor and read-only or guarded
Blocks selectable as user/supervisor and read-only or guarded
Page history Architecturally defined
Referenced and changed bits defined and maintained
Page address Architecturally defined
Translations stored as PTEs in hashed page tables in memory
translation
Page table size determined by mask in SDR1 register
TLBs Architecturally defined
Instructions for maintaining TLBs (tlble and tlbsync
instructions in 604)
604-specific
128-entry, two-way set associative ITLB
128-entry, two-way set associative DTLB
LRU replacement algorithm
Segment
de~ors
Architecturally defined Stored as segment registers on-chip (two Identical copies
maintained)
Page table search 604-specific The 604 performs the table search operation in hard-re.
support
Chapter 5. Memory Management 5-3