IBM PowerPC 604 User Manual page 245

0 2
3 4 5 6 7 8
•••I
O and
!=:::: ' : =:::=:::::::;::;;::j
-
..
C=:J
Fetch
H I
Decode
~ Dispatch
-
.•.
-
.
-
.
- - ··· .... ·:=.······· ...
- - --
- - ·
- - -
- - ·.··· ·
llllll!lllB
Execute
IIIIlIIII
Complete
- Write-Back
Figure 6-7. Instruction Timing-Cache Hit
9 10
The instruction timing for this example is described cycle-by-cycle as follows:
11
0. Two integer instructions (and and or) and two floating-point instructions (fadd and
fsub) are fetched in cycle 0. These were fetched from the second double-word
boundary in the instruction cache, so only two instructions can be fetched in the next
clock cycle.
1. In cycle 1, the last two instructions in the cache block (addc and subfc) are fetched,
while instructions 0-3 pass into the decode stage.
2. In cycle 2, the two integer add instructions (0 and 1) are dispatched, one to each of
the SCIUs. The fadd instruction (2) is dispatched to the FPU. The fsub instruction
cannot be dispatched, so is held in the dispatch stage until the next cycle.
Instructions 4 and
5
are in the decode stage.
Instructions 6-9 are fetched from a new cache block. Note that this is the typical,
and the most efficient, alignment for instructions fetching, allowing all eight
instruction in the cache block to be fetched in two cycles (four instructions per
cycle).
Chapter 6. Instruction Timing 6-19