IBM PowerPC 604 User Manual page 14

Paragraph
Number
7.2.4.2
7.2.4.2.1
7.2.4.2.2
7.2.4.3
7.2.4.3.1
7.2.4.3.2
7.2.4.4
7.2.4.5
7.2.4.6
7.2.4.7
7.2.4.7.1
7.2.4.7.2
7.2.4.8
7.2.5
7.2.5.1
7.2.5.2
7.2.5.2.1
7.2.5.2.2
7.2.5.3
7.2.5.3.1
7.2.5.3.2
7.2.6
7.2.6.1
7.2.6.2
7.2.6.3
7.2.6.3.1
7.2.6.3.2
7.2.7
7.2.7.1
7.2.7.1.1
7.2.7.1.2
7.2.7.2
7.2.7.2.1
7.2.7.2.2
7.2.7.3
7.2.7.4
7.2.8
7.2.8.1
7.2.8.2
7.2.8.3
7.2.9
7.2.9.1
7.2.9.2
Contents
CONTENTS
Title
Page
Number
Transfer Size (TSIZO--TSIZ2) ................................................................... 7-11
Transfer Size (TSIZO--TSIZ2)-0utput ................................................ 7-12
Transfer Size (TSIZO--TSIZ2}-Input ................................................... 7-12
Transfer Burst (TBST) ............................................................................... 7-13
Transfer Burst (TBST)-Output. ........................................................... 7-13
Transfer Burst (TBST}-lnput .............................................................. 7-13
Transfer Code (TCO--TC2)-0utput ......................................................... 7-13
Cache Inhibit (Cl)--Output ....................................................................... 7-14
Write-Through (WT)-Output .................................................................. 7-15
Global (GBL) ............................................................................................. 7-15
Global (GBL)-Output .......................................................................... 7-15
Global (GBL}-lnput ............................................................................ 7-15
Cache Set Element (CSEO-CSEl)-Output ............................................. 7-15
Address Transfer Termination Signals .......................................................... 7-16
Address Acknowledge (AACK}-Input. ................................................... 7-16
Address Retry (ARTRY) ........................................................................... 7-16
Address Retry (ARTRY)-Output ........................................................ 7-16
Address Retry (ARTRY}-lnput ........................................................... 7-17
Shared (SHD) ............................................................................................. 7-17
Shared (SHD)-Output ......................................................................... 7-17
Shared (SHD}-Input ............................................................................ 7-18
Data Bus Arbitration Signals ......................................................................... 7-18
Data Bus Grant (DBG}-Input .................................................................. 7-18
Data Bus Write Only (DBWO}-lnput ..................................................... 7-18
Data Bus Busy (DBB) ............................................................................... 7-19
Data Bus Busy (DBB)-Output ............................................................ 7-19
Data Bus Busy (DBB}-Input ............................................................... 7-19
Data Transfer Signals ..................................................................................... 7-20
Data Bus (DHO--DH31, DLO--DL31) ......................................................... 7-20
Data Bus (DHO--DH31, DLO--DL31)-0utput ...................................... 7-20
Data Bus (DHO--DH31, DLO--DL31}-lnput ........................................ 7-21
Data Bus Parity (DPO--DP7) ...................................................................... 7-21
Data Bus Parity (DPO--DP7)-0utput ................................................... 7-21
Data Bus Parity (DPO--DP7}-Input. ..................................................... 7-21
Data Parity Error (DPE)-Output ............................................................. 7-22
Data Bus Disable (DBDIS}-lnput ........................................................... 7-22
Data Transfer Termination Signals ................................................................ 7-22
Transfer Acknowledge (T A}-lnput ......................................................... 7-23
Data Retry (DRTRY}--Input .................................................................... 7-23
Transfer Error Acknowledge (TEA}-Input ............................................. 7-24
System Interrupt, Checkstop, and Reset Signals ........................................... 7-24
Interrupt (INT)--Input. .............................................................................. 7-25
System Management Interrupt (SMI}-Input ........................................... 7-25
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