IBM PowerPC 604 User Manual page 202

Effective Address
Generated
I-access D-access
Instruction
~truction
Translation Disabled Translation Enabled
(MSR(IR]
=
0) (MSR(IR]
=
1
............... Data
l?ata
~
Translation Disabled
Translation Enabled (MSR(DR] - O)
(MSR(DR]
=
1) -
Perfonn Real
Perfonn Real
Addressing Mode
Translation
Compare Address with
Instruction or Data BAT
Array (as appropriate)
Addressing Mode
Translation
BAT Array
Miss
Perfonn Address Translation
with Segment Desa;:>tor
(see Figure 5-6)
BAT Array (see The
Programming
Hit
~nmentsManual)
Access
_.,..6.-
Access
Protected Pennitted
(Access Fau§ Translate Address
Continue Access
to Memory
Subsystem
Figure 5-5. General Flow
of
Address Translation {Real Addressing Mode and Block)
Note that if the BAT array search results in a hit, the access is qualified with the appropriate
protection bits. If the access violates the protection mechanism, an exception (ISi or DSI
exception) is generated.
Implementation Note-The 604 BAT registers are not initialized by the hardware after the
power-up or reset sequence. Consequently, all valid bits in both instruction and data BAT
areas must be cleared before setting any BAT area for the first time. This is true regardless
of whether address translation is enabled. Also, software must avoid overlapping blocks
while updating a BAT area or areas. Even if translation is disabled, multiple BAT area hits
are treated as programming errors and can corrupt the BAT registers and produce
unpredictable results.
Chapter 5. Memory Management
5-13
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