Transfer Type (Tto-Tt4); Transfer Type - IBM PowerPC 604 User Manual

7 .2.4.1 Transfer Type (TTO-TT4)
The transfer type (TTO-TT4) signals consist of five input/output signals on the 604. For a
complete description of TTO-TT4 signals and for transfer type encodings, see Table 7-1.
7.2.4.1.1 Transfer Type (TTO-TT4)-0utput
Following are the state meaning and timing comments for the TTO-TT4 output signals on
the 604.
State Meaning
Asserted/Negated-Indicates the type of transfer in progress.
For direct-store operations these signals are part of the extended
address transfer code (XATC) along with TSIZ and TBST:
XATC(0-7)=TT(0-3)11TBSTllTSIZ(0-2).
Timing Comments Assertion/Negation/High Impedance-The same as AO-A31.
7.2.4.1.2 Transfer Type (TTO-TT4)-lnput
Following are the state meaning and timing comments for the TTO-TT4 input signals on
the 604.
State Meaning Asserted/Negated-Indicates the type of transfer in progress (see
Table 7-1). For direct-store operations, the TTO-TT3 signals form
part of the XATC and are snooped by the 604 if XATS is asserted.
Timing Comments Assertion/Negation-The same as AO-A31.
Table 7-1 describes the transfer encodings for a 604 bus master and the 60x bus
specification.
Table 7·1. Transfer Encoding for PowerPC 604 Processor Bus Master
no n1
TI'2
n3 n4
604 Bus Master
Transaction Transaction Source
Transaction
0
0 0
0
0 Clean block Address only Cache operation
0 0 1 0 0
Flush block Address only Cache operation
0
1
0
0
0
SYNC Address only Cache operation
0
1 1
0 0
Kill block Address only Store hit/shared or
cache operation
1
0 0 0 0
Ordered VO Address only elelo
operation
1 0 1
0 0
External control Single-beat ecowx
word
write
write
1 1 0 0 0
TlB invalidate Address only tlble
1 1 1
0 0
External control
Single-beat
eclwx
word
read read
0 0 0 0 1 lwanc Address only lwanc with cache hit
Reservation set
0 0 1
0
1 Reserved Address only NIA
7-10
PowerPC 604 RISC Microprocessor User's Manual