Scenarios For Referenced And Changed Bit Recording - IBM PowerPC 604 User Manual

5.4.1.3 Scenarios for Referenced and Changed Bit Recording
This section provides a summary of the model (defined by the OBA) that is used by
PowerPC processors for maintaining the referenced and changed bits. In some scenarios,
the bits are guaranteed to be set by the processor, in some scenarios, the architecture allows
that the bits may be set (not absolutely required), and in some scenarios, the bits are
guaranteed to not be set. Note that when the 604 updates the R and C bits in memory, the
accesses are performed as if MSR[DR]
=
0 and G
=
0 (that is, as nonguarded cacheable
operations in which coherency is required).
Table 5-8 defines a prioritized list of the R and C bit settings for all scenarios. The entries
in the table are prioritized from top to bottom, such that a matching scenario occurring
closer to the top of the table takes precedence over a matching scenario closer to the bottom
of the table. For example, if an stwcx. instruction causes a protection violation and there is
no reservation, the C bit is not altered, as shown for the protection violation case. Note that
in the table, load operations include those generated by load instructions, by the eciwx
instruction, and by the cache management instructions that are treated as a load with respect
to address translation. Similarly, store operations include those operations generated by
store instructions, by the ecowx instruction, and by the cache management instructions that
are treated as a store with respect to address translation.
Table 5-8. Model tor Guaranteed R and C Bit Settings
causes Setting of causes Setting
Priority Scenario
R Bit
Of C Bit
CEA 604 CEA 604
1 No-execute protection violation No No No No
2 Page protection violation Maybe Yes No No
3
Out-of-order instruction fetch or load operation Maybe No No No
4
Out-of-order store operation contingent on a branch, trap, Maybe No No No
sc or rfl instruction, or a possible exception
5
Out-of-order store operation contingent on an exception,
Maybe
No No No
other than a trap or ac instruction, not occurring
6 Zero-length load (lswx) Maybe No No No
7
Zero-length store (stswx) Maybe
1
No Maybe
1
No
8 Store conditional (stwcx.) that does not store Maybe
1
Yes
Maybe,
Yes
9 In-order instruction fetch
Yes 2
Yes No No
10
Load instruction or eclwx Yes Yes No No
11 Store instruction, ecowx, or dcbz instruction Yes Yes Yes Yes
Chapter 5. Memory Management 5-23
-