Sampled Data Address Register (Sda); Operand Conventions; Floating-Point Execution Models-Uisa - IBM PowerPC 604 User Manual

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If the perfonnance monitor interrupt was caused by something besides a threshold event,
the SIA contains the address of the last instruction completed during that cycle. The SDA
contains an effective address that is not guaranteed to match the instruction in the SIA. The
SIA and SDA are supervisor-level SPRs.
The SIA can be read by using the mfspr instruction and written to by using the mtspr
instruction (SPR 955).
2.1.2.4.4 Sampled Data Address Register (SDA)
The SDA contains the effective address of an operand of an instruction executing at or
around the time that the processor signals the perfonnance monitor interrupt condition. In
this case the SDA is not meant to have any connection with the value in the SIA. If the
perfonnance monitor interrupt was triggered by a threshold event, the SDA contains the
effective address of the operand of the SIA.
If the perfonnance monitor interrupt was caused by something other than a threshold event,
the SIA contains the address of the last instruction completed during that cycle. The SDA
contains an effective address that is not guaranteed to match the instruction in the SIA. The
SIA and SDA are supervisor-level SPRs.
The SDA can be read by using the mfspr instruction and written to by using the mtspr
instruction (SPR 959).
2.2 Operand Conventions
This section describes the operand conventions as they are represented in two levels of the
PowerPC architecture-VISA and VEA. Detailed descriptions are provided of conventions
used for storing values in registers and memory, accessing PowerPC registers, and
representation of data in these registers.
2.2.1 Floating-Point Execution Models-UISA
The IEEE 754 standard defines conventions for 64- and 32-bit arithmetic. The standard
requires that single-precision arithmetic be provided for single-precision operands. The
standard pennits double-precision arithmetic instructions to have either (or both)
single-precision or double-precision operands, but states that single-precision arithmetic
instructions should not accept double-precision operands.
• Double-precision arithmetic instructions may have single-precision operands but
always produce double-precision results.
• Single-precision arithmetic instructions require all operands to be single-precision
and always produce single-precision results.
For arithmetic instructions, conversion from double- to single-precision must be done
explicitly by software, while conversion from single- to double-precision is done implicitly
by the processor.
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PowerPC 604 RISC Microprocessor User's Manual