Execute Stage - IBM PowerPC 604 User Manual

6.2.1.1.4 Execute Stage
As shown in Figure 6-3, after an instruction passes through the common stages of fetch,
decode, and dispatch, they are passed
to
the appropriate execution unit where they are said
to be in execute stage. Note that the time that an instruction spends in the execute stage
varies depending on the execution unit For example, the floating-point unit has a fully-
pipelined, three-stage execution unit, so most floating-point instructions have a three-cycle
execute latency, regardless whether they are single- or double-precision. Some instructions,
such as integer divides, must repeat some stages in order
to
calculate the correct result.
The execute stage executes the instruction selected in the dispatch stage, which may come
from the reservation stations or from instructions arriving from dispatch. At the end of
execute stage, the execution unit writes the results
into
the appropriate rename buffer entry,
and notifies the complete stage that the instruction has finished execution.
If
it is determined that the direction of a branch instruction was mispredicted in an earlier
stage, the instructions from the mispredicted pith BJ"e flushed and fetching resumes at the
correct address.
If
an instruction causes an exception, the execution unit reports the exception
to
the
complete stage and continues executing instructions regardless of the exception. Under
certain conditions, results can write directly into the register file and bypass the rename
registers.
Most instructions that execute in the MCIU can finish execution and complete in the same
cycle. These include the following:
• Integer divide, multiply when OE = 0
• All mfspr
• All mtspr instructions except when
LR/CTR
is involved
Note that all instructions that execute in the MCIU can complete during the same cycle in
which they finish executing except for the following:
• Instructions that change OV or CA (OE=
1)
• Move
to
CTR/LR
instructions because they are not execution-serialized
An example of one of these instructions,
mulli,
is shown in the instruction timing examples
in Figure 6-9 through Figure 6-12.
An
instruction can finish execution
and
complete only
if
it is
the
first instruction
to
complete. Whether an instruction is able
to
complete in the
same cycle in which it finishes execution is also subject to the normal considerations that
affect execution and completion.
For more information about individual execution units, see Section 6.5, "Execution Unit
Tllllings."
6·10 PowerPC 604 RISC Mlcroproceuor U..r'• Manual