Direct-Store Transaction Protocol Details - IBM PowerPC 604 User Manual

The load request direct-store operation has no analogous store operation; it infonns the
addressed BUC of the total number of bytes of data that the BUC must provide to the 604
on the subsequent load immediate/load last operations. For direct-store load accesses, the
simplest, 32-bit (or fewer) data transfer sequence is as follows:
LOAD REQUEST
•
•
WAD LAST
•
•
LOAD REPLY(from BUC)
However, if more data is involved in the direct-store access, there will be one or more load
immediate operations. The BUC can detect when the last data is being transferred by
looking for the load last opcode, as seen in the following sequence:
WAD REQUEST
•
•
LOADIMM(s)
•
•
LOAD LAST
•
•
LOAD REPLY
Note that three of the seven defined operations are address-only transactions and do not use
the data bus. However, unlike the memory transfer protocol, these transactions are not
broadcast from one master to all snooping devices. The direct-store address-only
transaction protocol strictly controls communication between the 604 and the BUC.
8.6.2 Direct-Store Transaction Protocol Details
As mentioned previously, there are two address-bus beats corresponding to two packets of
information about the address. The two packets contain the sender and receiver tags, the
address and extended address bits, and extra control and status bits. The two beats of the
address bus (plus attributes) are shown at the top of Figure 8-23 as two packets. The first
packet, packet 0, is then expanded to depict the XATC and address bus information in
detail.
8-42 PowerPC 604 RISC Microprocessor User's Manual