IBM PowerPC 604 User Manual page 21

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CONTENTS
Title
Page
Number
2-32 System Linkage lnstruction-UISA ..................................................................... 2-46
2-33 Move to/from Condition Register Instructions ..................................................... 2-46
2-34 Move to/from Special-Purpose Register Instructions (UISA) .............................. 2-47
2-35 Memory Synchronization lnstructions-UISA .................................................... 2-47
2-36 Move from Time Base Instruction ....................................................................... 2-48
2-37 Memory Synchronization Instructions-VEA ..................................................... 2-49
2-38 User-Level Cache Instructions ............................................................................. 2-51
2-39 External Control Instructions ............................................................................... 2-52
2-40 System Linkage Instructions-CEA .................................................................... 2-52
2-41 Move to/from Machine State Register Instructions .............................................. 2-53
2-42 Move to/from Special-Purpose Register Instructions (OEA) ............................... 2-53
2-43 SPR Encodings for 604-Defined Registers (mfspr) ............................................ 2-53
2-44 Cache Management Supervisor-Level Instruction ............................................... 2-54
2-45 Segment Register Manipulation Instructions ....................................................... 2-55
2-46 Translation Lookaside Buffer Management Instruction ....................................... 2-56
3-1 Memory Coherency Actions on Load Operations .................................................. 3-8
3-2 Memory Coherency Actions on Store Operations .................................................. 3-9
3-3 MESI State Definitions ......................................................................................... 3-11
3-4 Response to Bus Transactions .............................................................................. 3-20
3-5 604 Bus Operations Initiated by Cache Control Instructions ............................... 3-23
3-6 Cache Actions ....................................................................................................... 3-24
4-1 Exception Classifications ....................................................................................... 4-3
4-2 Exceptions and Conditions-Overview ................................................................. 4-3
4-3 MSR Bit Settings .................................................................................................... 4-7
4-4 IEEE Floating-Point Exception Mode Bits ............................................................ 4-9
4-5 MSR Setting Due to Exception ............................................................................ 4-12
4-6 System Reset Exception-Register Settings ........................................................ 4-13
4-7 Machine Check Enable Bits ................................................................................. 4-14
4-8 Machine Check Exception-Register Settings .................................................... 4-15
4-9 Other MMU Exception Conditions ....................................................................... 4-16
4-10 Trace Exception-SRRl Settings ......................................................................... 4-19
5-1 MMU Feature Summary ......................................................................................... 5-3
5-2 Access Protection Options for Pages .................................................................... 5-11
5-3 Translation Exception Conditions ........................................................................ 5-17
5-4 Other MMU Exception Conditions for the PowerPC 604 Processor ................... 5-18
5-5 PowerPC 604 Microprocessor Instruction Summary-Control MMUs .............. 5-19
5-6 PowerPC 604 Microprocessor MMU Registers ................................................... 5-19
5-7 Search Operations to Update History Bits-TLB Hit Case ................................ 5-21
5-8 Model for Guaranteed R and C Bit Settings ......................................................... 5-23
6-1 Execution Latencies and Throughputs ................................................................... 6-7
6-2 Instruction Execution Timing ............................................................................... 6-46
7-1 Transfer Encoding for PowerPC 604 Processor Bus Master ................................ 7-10
7-2 Data Transfer Size ................................................................................................ 7-12
xviii PowerPC 604 RISC Microprocessor User's Manual