Cache Inhibit (Cl)-Output - IBM PowerPC 604 User Manual

Table 7·3. Encodings for TCO-TC2 Signals (Continued)
TranSfer
Type
WI'
TCO TC1 TC2 Transaction
Write-with-kiO 0
1
0 0
Snoop push
(read-with-Intent-to-modify)
WrHe-with-klD
0 0 0 0
Snoop
push
(clean operation)
Write-with-kill 0
1
0 0
Snoop push
(flush operation)
KiUblock
x
1 0 0
K"dl block de-allocate
(dcbl)
KiU block 1 0 0 0
KOi block
&
allocate
with no cast-out (dcbz)
KID block 1 0 0 1 KOi block & allocate
with cast-out
(dcbZ)
KiOblock 1
0 0 0
KDlblock
Write to shared block
Read,
W3
0
x
0
Data read
with no
cast-out
Read
w
0
x
1 Data read
with
cast-out
Read
w
1
x
0
Instruction read
ICBI
x
1
0 0
Kill block and de-allocate
(lcbl)2
Note:
1. · 1ndudes both ordinary and atomic read and read-with-intent-to-modify operations.
2. ICBI operation
is
distinguished from kiU block by assertion of TT4 bit. ·
3.
W
= write-through bit from translation.
The value shown in the
WT
column reflects the actual logic value seen on the
WT
input signal.
7 .2.4.5 cache Inhibit (Cl)-Output
The cache inhibit (Cl) signal is an output signal on the 604. Following are the state meaning
and timing comments for the CI signal.
State Meaning
Asserted-Indicates that a single-beat transfer will not
be
cached,
reflecting the setting of the I bit for the block or page that contains
the address of the current transaction.
· Negated-Indicates that a burst transfer will allocate a line in the 604
data
cache.
Timing Comments Assertion/Negation-The same as AO-A31.
High Impedance-The same as AO-A31.
7-14
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