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12.
Implementation Dependent Instructions
This chapter describes all the A2 core instructions implemented that are not part of Power ISA or that are
implementation dependent.
12.1 Miscellaneous
12.1.1 Attention (attn)
0
0
6
For purposes of hardware debugging, the processor supports a special, implementation-dependent instruc-
tion for signaling an "attention" signal to system-level hardware, which is beyond the scope of this document.
This instruction is per thread and causes the following sequence:
1. A normal CSI event is generated for the thread issuing the instruction.
2. The instructions following the attention instruction are flushed for the thread issuing the instruction.
3. A dispatch stall is enabled so that no further instructions can be dispatched for the thread issuing the
instruction.
4. An attention signal, if enabled by the corresponding Special Attention Register (SPATTN) mask bit, is sent
to system-level hardware.
The attn instruction has the following definition:
• The immediate field (I) has no effect on the operation of this instruction.
• If CCR2[en_attn] = 1 (support processor attention enable bit is set), this instruction causes all preceding
instructions to run to completion, the machine to quiesce, and a bit in the Special Attention Register
(SPATTN) to be set. If enabled by the corresponding SPATTN register mask bit, a support processor
attention signal is be asserted.
• If CCR2[en_attn] = 0 (support processor attention enable bit is not set), this instruction causes an illegal
instruction type of program interrupt.
Version 1.3
October 23, 2012
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Implementation Dependent Instructions
Page 481 of 864
User's Manual
A2 Processor
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