Address Bus Busy (Abb); Address Bus Busy (Abb)-Output - IBM PowerPC 604 User Manual

of the negation of BG because during the previous cycle BG
indicated to the 604 that it was free to take mastership (if qualified).
7.2.1.3 Address Bus Busy (ABB)
The address bus busy (ABB) signal is both an input and an output signal.
7.2.1.3.1 Address Bus Busy (ABB)-Output
Following are the state meaning and timing comments for the ABB output signal.
State Meaning
Asserted-Indicates that the 604 is the address bus master. See
Section 8.3.1, "Address Bus Arbitration."
Negated-Indicates that the 604 is not using the address bus. If ABB
is negated during the bus clock cycle following a qualified bus grant,
the 604 did not accept mastership, even if BR was asserted. This can
occur if a potential transaction is aborted internally before the
transaction is started.
Timing Comments
Assertion-Occurs on. the bus clock cycle following a qualified BG
that is accepted by the processor (see Negated).
Negation-Occurs on the bus clock cycle following the assertion of
AACK. If ABB is negated during the bus clock cycle following a
qualified bus grant, the 604 did not accept mastership, even if BR
was asserted.
High Impedance-Occurs one-half bus cycle (two-thirds bus cycle
when using 3: 1 clock mode, and one-third bus cycle when using 3:2
bus ratio) after ABB is negated.
7.2.1.3.2 Address Bus Busy (ABB)-lnput
Following are the state meaning and timing comments for the ABB input signal.
State Meaning
Asserted-Indicates that the address bus is in use. This condition
effectively blocks the 604 from assuming address bus ownership,
regardless of the BG input; see Section 8.3.1, "Address Bus
Arbitration." Note that the 604 will not take the address bus for the
sequence of cycles beginning with TS and ending with
AACK;
thus
effectively making the use of ABB optional, provided that other bus
masters respond in the same way.
Negated-Indicates that the address bus is not owned by another bus
master and that it is available to the 604 when accompanied by a
qualified bus grant.
Timing Comments
Assertion-May occur when the 604 must be prevented from using
the address bus (and the processor is not currently asserting ABB).
Negation-May occur whenever the 604 can use the address bus.
Chapter 7. Signal Descriptions 7-5