Cache Miss Timing Example - IBM PowerPC 604 User Manual

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6.4.2.2 Cache Miss Timing Example
Figure 6-8 illustrates the timing for a cache miss using the following code sequence.
add
fadd
add
fadd
br
add
fsub
add
fsub
add
fadd
Note that this example asswnes a best-case scenario.
0
I••• I
Io
add
I
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
I
I
I
I
I
I
I
I
----<~
Address :
.----..
-.....,...-~--.
I
t---5add-I -+--I
----1- · •
· · · · · · · · · · · · · · · ~
l61subl
h? ••
= . , ....
I I
l7addl • • • • • • • • • • • • • • • • • • ~ lllll~l-
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Fetch . . Execute
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I d
Decode
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Complete
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Dispatch - Write-Back
I 9add Ir
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Figure 6-8. Instruction Timing-Instruction Cache Miss (BT AC Hit)
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PowerPC 604 RISC Microprocessor User's Manual