Floating-Point Status And Control Register (Fpscr); Machine State Register (Msr); Segment Registers (Srs); Special-Purpose Registers (Sprs) - IBM PowerPC 604 User Manual

1.3.2.4 Floating-Point Status and Control Register (FPSCR)
The floating-point status and control register (FPSCR) is a user-level register that contains
all exception signal bits, exception summary bits, exception enable bits, and rounding
control bits needed for compliance with the IEEE 754 standard.
1.3.2.5 Machine State Register (MSR)
The machine state register (MSR) is a supervisor-level register that defines the state of the
processor. The contents of this register are saved when an exception is taken and restored
when the exception handling completes. The 604 implements the MSR as a 32-bit register;
64-bit PowerPC processors use a 64-bit MSR that provides a superset of the 32-bit
functionality.
1.3.2.6 Segment Registers (SRs)
For memory management, 32-bit PowerPC implementations use sixteen 32-bit segment
registers (SRs).
1.3.2.7 Special-Purpose Registers (SPRs)
The PowerPC operating environment architecture defines numerous special-purpose
registers that serve a variety of functions, such as providing controls, indicating status,
configuring the processor, and performing special operations. Some SPRs are accessed
implicitly as part of executing certain instructions. All SPRs can
be
accessed by using the
move to/from SPR instructions, mtspr and mfspr.
In the 604, all SPRs are 32 bits wide.
1.3.2.7.1 User-Level SPRs
The following SPRs are accessible by user-level software:
• Link register (LR)-The link register can
be
used
to
provide the branch target
address and to hold the return address after branch and link instructions. The LR is
32 bits wide.
• Count register (CTR)-The CTR is decremented and tested automatically as a result
of branch and count instructions. The CTR is 32 bits wide.
• XER-The 32-bit XER contains the integer carry and overflow bits.
• The time base registers (TBL and TBU) can
be
read by user-level software, but can
be
written
to
only by supervisor-level software.
1.3.2.7.2 Supervisor-Level SPRs
The 604 also contains SPRs that can
be
accessed only by supervisor-level software. These
registers consist of the following:
• The 32-bit data DSISR defines the cause of OSI and alignment exceptions.
• The data address register (DAR) is a 32-bit register that holds the address of an
access after an alignment or OSI exception.
Chapter 1.
Overview 1-23