Reset Signals; Hard Reset; Soft Reset - IBM PowerPC 604 User Manual

Timing Comments Assertion-May occur at any time and may
be
asserted
asynchronously to the 604 input clocks.
="""""""""""""
Negation-Is negated upon assertion of HRESET.
7.2.9.6 Reset Signals
There are two reset signals on the 604-hard reset (HRESET) and soft reset (SRESET).
Descriptions of the reset signals are as follows:
7.2.9.6.1 Hard Reset (HRESET)-lnput
The hard reset (HRESET) signal is input only and must
be
used at power-on
to
properly
reset the processor. Following are the state meaning and timing comments for the HRESET
signal.
State Meaning Asserted-Initiates a complete hard reset operation when this input
transitions from asserted to negated. Causes a reset exception as
described in Section 4.5.1, "System Reset Exception (Ox.00100)."
Output drivers are released
to
high impedance within five clocks
after the assertion of HRESET.
Negated-Indicates that normal operation should proceed. See
Section 8.8.3, "Reset Inputs."
Timing Comments Assertion-May occur at any time and may
be
asserted
asynchronously to the 604 input clock; must
be
held asserted for a
minimum of 255 clock cycles.
Negation-May occur any time after the minimum reset pulse width
has
been met.
If deterministic cycle sequencing is required (for example, in multiple processor systems
operating in lock step}, the HRESET signal should be asserted and negated synchronously
with the SYSCLK signal. The HRESET signal has additional functionality in certain test
modes.
7.2.9.6.2 Soft Reset (SRESET)-lnput
The soft reset (SRESET) signal is input only. Following are the state meaning and timing
comments for the SRESET signal.
State Meaning
Asserted- Initiates processing for a reset exception as described in
Section 4.5.1, "System Reset Exception (Ox.00100)."
Negated-Indicates that normal operation should proceed. See
Section 8.8.3, "Reset Inputs."
Timing Comments Assertion-May occur at any time and may
be
asserted
asynchronously to the 604 input clock. The SRESET input is
negative edge-sensitive.
Negation-May
be
negated two bus cycles after assertion.
Chapter 7. Signal Descriptions 7-27