Threshold Events; Threshold Conditions; Lateral L2 Cache Intervention - IBM PowerPC 604 User Manual

9.1.2.2 Threshold Events
These PMCl events are numbers 9, 10, 23, and 24. These events monitor load and store
misses (with and without lateral L2 intervention). Only "marked" loads and stores (loads
and stores at queue position 0) are monitored. See Section 9.1.2.2.1, "Threshold
Conditions," for more information.
When a marked operation is detected, the SDA is updated with the effective address. When
the marked instruction finishes executing, the SIA will be updated with the address of that
instruction. Thus, when a PMI is signaled (as a result of a threshold event) the SIA and SDA
contains the exact SIA and SDA belonging to the instruction that caused PMCl to become
negative; see Section 9.1.2.2.3, "Warnings," for further information.
9.1.2.2.1 Th res hold Conditions
The ability to generate a PMI based on a threshold condition makes it possible to
characterize Ll data cache misses. Specifically, the programmer should be able to identify
(through repeated runs and sampling) the time distribution required to satisfy L1 cache
misses. For example, if PMCl is counting load misses and the threshold is set to two
(cycles), only load misses taking more than two cycles are counted. Repeated runs with
different threshold values would allow construction of a load-miss distribution chart.
When a load (or store) miss arrives in the load/store queue, the threshold control logic
begins decrementing. For each cycle that passes, the threshold value in a shadow register
(obtained from MMCRO[l0-15]) is decremented The threshold is exceeded when this
value reaches 0, at which point the PMCl count is updated.
While servicing the load/store misses, the SIA and SDA registers are updated to the exact
instruction and data addresses at the time an interrupt condition occurs. Thus, at the end of
each threshold load or store operation, the SIA contains the address of the instruction that
was last monitored, and the SDA contains the address of the data of the same instruction.
9.1.2.2.2 Lateral L2 Cache Intervention
A load or store operation that misses in the L1 cache can receive its data from one of several
memory devices. In a uniprocessor system, the data would likely come an L2 cache, or from
main memory if no L2 cache is present. In a multiprocessor system, the data can originate
from the L2 cache connected to another 604 (that is, a lateral L2 cache), in which case, the
L2 controller asserts an intervention signal (L2_INn used by the performance monitor.
This signal is useful when tracking memory latencies in a SMP system. For information
about the L2_intervention signal, see Section 7.2.10.3, "L2 Intervention
(L2_JNn-lnput."
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PowerPC 604 RISC Microprocessor User's Manual