IBM PowerPC 604 User Manual page 340

When the 604 is not the address bus master, GBL is an input. The 604 snoops a transaction
if TS and GBL are asserted together in the same bus clock cycle (this is a qualified snooping
condition). No snoop update
to
the 604 cache occurs if the snooped transaction is not
marked global. This includes invalidation cycles.
When the 604 detects a qualified snoop condition, the address associated with the TS is
compared against the data cache tags through a dedicated cache tag port. Snooping
completes if no hit is detected. If, however, the address hits in the cache, the 604 reacts
according to the MESI protocol shown in Figure 8-15, assuming the WIM bits are set to
write-back mode, caching allowed, and coherency enforced (WIM
=
001).
Note that write hits to clean lines of nonglobal pages do not generate invalidate broadcasts.
There are several types of bus transactions that involve the movement of data that can no
longer access the TLB M-bit (for example, replacement cache block copy-back, or a snoop
push). In these cases, the hardware cannot determine whether the cache block was
originally marked global; therefore, the 604 marks these transactions as nonglobal to avoid
retry deadlocks.
The 604's on-chip data cache is implemented as a four-way set-associative cache. To
facilitate external monitoring of the internal cache tags, the cache set element (CSEO-
CSEl) signals indicate which sector of the cache set is being replaced on read operations
(including RWITM). Note that these signals are valid only for 604 burst operations; for all
other bus operations, the CSEO-CSEl signals should be ignored.
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PowerPC 604 RISC Microprocesaor User's Manual