IBM PowerPC 604 User Manual page 262

Risc
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These subunits handle all of
the
one-cycle arithmetic instructions. Only one subunit in each
SCIU can obtain and execute an instruction at a time.
ns
on 1spa1
I
lructi
tch
B
uses
GPR
Operand
Buses
Result Buses
1
r--.,
Reservation Station
-
&>
::I
Rotate/Shift/
i....-
Adder/
~
Logic
I
CTLZ
Comparator
-
i
cs·
,
j_
\
3:1 MUX
I...
j
-
'-...)
Figure &-14. SCIU Block Diagram
The MCIU, which handles all integer multiple-cycle integer insttuctions, consists of a 32-
bit integer multiplier/divider subunit The multiplier supports early exit on 32 x 16-bit
operations.
In
addition
the
MCIU executes all mfspr and mtspr insttuctions.
6-36
PowerPC 604 RISC Microproceaeor Ueer'e Manual

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