IBM PowerPC 604 User Manual page 217

5-28
Effective Address
Generated
Page Acld1'8ss
Translation
Generate 52-Bit
Virtual Addl'8ss from
Segment Desci;>tor
Compal'8 Virtual
Acld1'8ss with TlB Entries
Instruction Fetch with
N bit Set in Segment
Descriptor
dcbz Instruction
withWorl=1
otherwise
[
( Alignment Exception )
Check Page Memory
Protection Violation Conditions
(see The Programming
Environments Manualj
Access Penniltad Access Prohibited
(see
The
Programming
EnVlronmfltlts
Manual)
--~·~
PTE [CJ
=
0 otherwise
Page Memory
Protection Violation
Invalidate TlB entry
Page Table
Search
~ration
(See f"igul'8 5-9)
PAO-PA31+-RPNllA20-A31
Continue Access to Memory
Subsystem with WIMG bits
from PTE
Figure 5-8. Page Address Translation Flow-TLB HH
PowerPC 604 RISC Mlcroproceeeor Ueer'e Manuel