Data Cache Organization - IBM PowerPC 604 User Manual

As shown in Figure 3-2, the instruction cache is connected to the bus interface unit (BIU)
with a 64-bit bus; likewise, the data cache is connected both to the BIU and
the
load/store
unit (LSU) with a 64-bit bus. The 64-bit bus allows two instructions to be loaded into the
instruction cache or a double word (for example, a double-precision floating-point operand)
to be loaded into
the
data cache in a single clock. The instruction cache provides a 128-bit
interface to the instruction fetcher, so four instructions can be made available to the
instruction unit in a single clock cycle.
Instruction Unit
Instructions (0-127)
Instruction Cache
16-Kbyte
Four-Way SetAssociative
Instructions
(0-63)
EA: Effective Address
PA: Physical Address
EA(20-31)
Cache
Tags
PA(0-19)
PA(0-31)
Cache
Tags
MMU/Bus Interface Unit (BIU)
Figure 3·2. cache Integration
3.1 Data Cache Organization
Load/Store Unit (LSU)
Data(0-63)
Data Cache
16-Kbyte
Four-Way SetAssociative
Data(0-63)
As shown .in Figure 3-2, the physically-addressed data cache lies between
the
load/store
instruction unit (LSU) and the bus interface unit (BIU), and provides the ability to read and
write data in memory by reducing the number of system bus transactions required for
execution of load/store instructions.
The LSU transfers data between the data cache and
the
result bus, which routes data to the
other execution units. The LSU supports the address generation and all
the
data alignment
to and from the data cache. The LSU also handles other types of instructions that access
memory, such as cache control instructions, and supports out-of-order loads and stores
while ensuring the integrity of data.
Chapter 3. Ceche and Bus Interlace Unit Op•ation
3-3