Performance Monitor Counter Registers (Pmcl And Pmc2) - IBM PowerPC 604 User Manual

Table 2-4. MMCRO Bit Settings (Continued)
Bit Name Description
9 INTONBITTRANS Cause interrupt signalling on bit transition (identified in RTCSELECT) from off to
on
0 Do not allow interrupt signal ii chosen bit transitions.
1 Signal interrupt if chosen bit transitions.
Software is responsible for setting and clearing INTONBITTRANS.
10-15 THRESHOLD Threshold value. All 6 bits are supported by the 604; allowing threshold values
from 0 to 63. The intent of the THRESHOLD support is to be able to characterize
L 1 data cache misses.
16
PMC1 INTCONTROL Enable interrupt signaling due to PMC1 counter negative.
0
Disable PMC1 interrupt signaling due to PMC1 counter negative
1 Enable PMC1 Interrupt signaling due to PMC1 counter negative
17 PMC21NTCONTROL Enable interrupt signalling due to PMC2 counter negative. This signal overrides
the setting of DISCOUNT.
0 Disable PMC2 interrupt signaling due to PMC2 counter negative
1 Enable PMC2 Interrupt signaling due to PMC2 counter negative
18
PMC2COUNTCTL May be used to trigger counting of PMC2 after PMC1 has become negative or
after a performance monitoring interrupt is signaled.
0 Enable PMC2 counting
1 Disable PMC2 counting until PMC1 bit
O
is set or until a performance monitor
interrupt is signaled
This signal can be used to trigger counting of PMC2 after PMC1 has become
negative. This provides a triggering mechanism for counting after a certain
condition occurs or after a preset time has elapsed.
It
can be used to support
getting the count associated with a specific event.
19-25 PMC1SELECT PMC1 input selector, 128 events selectable; 25 defined. See Table 2-5.
26-31 PMC2SELECT
PMC2 input selector, 64 events selectable; 21 defined. See Table 2-6.
2.1.2.4.2 Performance Monitor Counter Registers (PMC1 and PMC2}
PMCl and PMC2 are 32-bit counters that can be programmed to generate interrupt signals
when they are negative. Counters are considered to be negative when the high-order bit (the
sign bit) becomes set; that is, they reach the value 2147483648 (Ox8000_0000). However,
an interrupt is not signaled unless both PCMn[INTCONTROL] and MMCRO[ENINT] are
also set.
Note that the interrupts can be masked by clearing MSR[EE]; the interrupt signal condition
may occur with MSR[EE] cleared, but the interrupt is not taken until the EE bit is set.
Setting MMCRO[DISCOUNT] forces the counters stop counting when a counter interrupt
occurs.
PMCl and PMC2 are SPRs 953 and 954, respectively, and can be read and written to by
using the mfspr and mtspr instructions. Software is expected to use the mtspr instruction
to explicitly set the PMC register to non-negative values. If software sets a negative value,
an erroneous interrupt may occur. For example, if both PCMn[INTCONTROL] and
MMCRO[ENINT] are set and the mtspr instruction is used to set a negative value, an
interrupt signal condition may be generated prior to the completion of the mtspr and the
Chapter 2. PowerPC 604 Processor Programming Model
2-13
-