Execution Synchronization; Instruction-Related Exceptions - IBM PowerPC 604 User Manual

• Previous insuuctions complete execution in the context (privilege, protection, and
address translation) under which they were issued.
• The insuuctions following the sc or rfi insuuction execute in the context established
by these insuuctions.
2.3.2.4.2 Execution Synchronization
An insuuction is execution synchronizing if all previously initiated insuuctions appear to
have completed before the insuuction is initiated or, in the case of sync and isync, before
the insuuction completes. For example, the Move
to
Machine State Register (mtmsr)
insuuction is execution synchronizing. It ensures that all preceding insuuctions have
completed execution and will not cause an exception before the insuuction executes, but
does not ensure subsequent insuuctions execute in the newly established environment For
example, if the mtmsr sets the MSR[PR] bit, unless an isync immediately follows· the
mtmsr insuuction, a privileged insuuction could be executed or privileged access could be
performed without causing an exception even though the MSR[PR] bit indicates user mode.
2.3.2.4.3 Instruction-Related Exceptions
There are two kinds of exceptions in the 604-those caused directly by the execution of an
insuuction and those caused by an asynchronous event (or interrupts). Either may cause
components of the system software
to
be invoked.
Exceptions can be caused directly by the execution of an insuuction as follows:
• An attempt to execute an illegal insuuction causes the illegal insuuction (program
exception) handler
to
be invoked. An attempt by a user-level program
to
execute the
supervisor-level insuuctions listed below causes the privileged insuuction (program
exception) handler
to
be invoked. The 604 provides the following supervisor-level
insuuctions: dcbi, mfmsr, mfspr, mfsr, mfsrin, mtmsr, mtspr, mtsr, mtsrin, rfi,
tlbie, and tlbsync. Note that the privilege level of the mfspr and mtspr insuuctions
depends on the SPR encoding.
• An attempt to access memory that is not available (page fault) causes the ISi
exception handler to be invoked.
• An attempt to access memory with an effective address alignment that is invalid for
the insuuction causes the alignment exception handler
to
be invoked.
• The execution of an sc insuuction invokes the system call exception handler that
permits a program
to
request the system
to
perform a service.
• The execution of a trap insuuction invokes the program exception trap handler.
• The execution of a floating-point insuuction when floating-point insuuctions are
disabled invokes the floating-point unavailable handler.
• The execution of an insuuction that causes a floating-point exception while
exceptions are enabled in the MSR invokes the program exception
handler~
Exceptions caused by asynchronous events are described in Chapter 4, "Exceptions."
Chapter 2. PowerPC 604 Processor Programming Model
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