Tlb Entry Invalidation; Powerpc 604 Microprocessor Instruction Summary-Control Mmus; Powerpc 604 Microprocessor Mmu Registers - IBM PowerPC 604 User Manual

Table
5-5
summarizes 604 insttuctions that specifically control the MMU.
Table 5-5. PowerPC 604 Microprocessor Instruction Summary-Control MMUs
Instruction Description
mtsrSR,rS Move to Segment Register
SR[SR#)+- rs
mtsrln rS,rB Move to Segment Register Indirect
SR[rB(0-3D+-rS
mfsrrD,SR Move from Segment Register
rD+-SR[SR#)
mfsrln rD,rB Move from Segment Register Indirect
rD+-SR(rB(0-3D
tlble rB • Execution al this instruction causes all entries In the congruence class corresponding to the EA to
be invalidated in the processor executing the instruction and in the other processors attached to
the same bus.
Software must ensure that instruction fetches or memory references to the virtual pages specified
by the tlble instruction have been completed prior to executing the tlble instruction.
tlbsync • The tlbsync operation appears on the bus as a distinct operation that causes synchronization al
snooped tlble instructions.
•These instructions are defined by the PowerPC architect1Jf8, but are optional.
Table 5-6 summarizes the registers that the operating system uses
to
program the 604
MMUs. These registers are accessible to supervisor-level software only. These registers are
described in Chapter 2, "PowerPC 604 Processor Programming Model."
Table 5-6. PowerPC 604 Microprocessor MMU Registers
Register
Description
Segment registers The sixteen 32-bit segment registers are present only in 32-bit Implementations of
(SRO-SR15)
the PowerPC architecture. The fields in the segment register are interpreted
differently depending on the value al bit 0. The segment registers are accessed by
the mtsr, mtsrln, mfsr, and mfsrtn Instructions.
BAT registers
There are 16 BAT registers, organized as four pairs of instruction BAT registers
(IBATOU-IBAT3U,
(IBATOU-IBAT3U paired with IBATOL-IBAT3L) and four pairs of data BAT registers
IBATOL-IBAT3L,
(DBATOU-DBAT3U paired with DBATOL-DBAT3L). The BAT registers are defined
DBATOU-OBAT3U,and as 32-bil registers in 32-bit implementations. These are special-purpose registers
DBATOL-OBAT3L)
that are accessed by the mtspr and mfspr instructions.
SDR1
The SDR1 register specifies the variables used in accessing the page tables In
memory. SDR1 is defined as a 32-bit register for 32-bit implementations. This
special-purpose register is accessed by the mtspr and mfspr instruc:tions.
5.1.9 TLB Entry Invalidation
For PowerPC processors such as the 604 that implement TLB sttuctures
to
maintain
on-chip copies of the PTEs that are resident in physical memory, the optional TLB
Invalidate Entry (tlbie) insttuction provides a way
to
invalidate the TLB entries.
Chapter 5. Memory Management
5-19