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1.3 PowerPC 604 Microprocessor Execution Model
This section describes the following characteristics of the 604's execution model:
•
The PowerPC architecture
•
The 604 register set and programming model
•
The 604 instruction set
•
The 604 exception model
•
Instruction timing on the 604
1.3.1 Levels of the PowerPC Architecture
The PowerPC architecture is derived from the IBM POWER Architecture
TM
(Performance
Optimized with Enhanced RISC architecture). The PowerPC architecture shares the
benefits of the POWER architecture optimized for single-chip implementations. The
architecture design facilitates parallel instruction execution and is scalable to take
advantage of future technological gains.
The PowerPC architecture consists of the following layers, and adherence to the PowerPC
architecture can be measured in terms of which of the following levels of the architecture
is implemented. For example, if a processor adheres to the virtual environment architecture,
it is assumed that it meets the user instruction set architecture specification.
•
PowerPC user instruction set architecture (UISA)-The UISA defines the level of
the architecture to which user-level software must conform. The UISA defines the
base user-level instruction set, user-level registers, data types, memory conventions,
and the memory and programming models seen by application programmers. Note
that the PowerPC architecture refers to user level as problem state.
•
PowerPC virtual environment architecture (VEA)-The VEA, which is the smallest
component of the Power PC architecture, defines additional user-level functionality
that falls outside typical user-level software requirements. The VEA describes the
memory model for an environment in which multiple processors or other devices
can access external memory, defines aspects of the cache model and cache control
instructions from a user-level perspective. The resources defined by the VEA are
particularly useful for managing resources in an environment in which other
processors and other devices can access external memory.
Implementations that conform to the PowerPC VEA also adhere to the UISA, but
may not necessarily adhere to the OEA.
•
PowerPC operating environment architecture (OEA)-The OEA defines
supervisor-level resources typically required by an operating system. The OEA
defines the PowerPC memory management model, supervisor-level registers, and
the exception model. Note that the PowerPC architecture refers to the supervisor
level as privileged state.
Implementations that conform to the PowerPC OEA also conform to the PowerPC
UISA and VEA.
Chapter 1. Overview
1-19
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