Data Bus Arbitration Signals; Data Bus Grant; Data Bus Write Only - IBM PowerPC 604 User Manual

7.2.5.3.2 Shared {SHD}-lnput
Following are the state meaning and timing comments for the SHD input signal.
State Meaning Asserted-If ARTRY is not asserted, indicates that for a self-
generated transaction the 604 must allocate the incoming cache
block as shared-unmodified.
Negated-If ARTRY is not asserted, indicates that the address for
the current transaction is not in any other cache.
Timing Comments Assertion/Negation-The same as ARTRY.
7.2.6 Data Bus Arbitration Signals
Like the address bus arbitration signals, data bus arbitration signals maintain an orderly
process for determining data bus mastership. Note that there is no data bus arbitration signal
equivalent
to
the address bus arbitration signal BR (bus request), because, except for
address-only transactions, TS and XATS imply data bus requests. For a detailed description
on how these signals interact, see Section 8.4.1, "Data Bus Arbitration."
One special signal, DBWO, allows the 604
to
be configured dynamically
to
write data out
of order with respect to read data. For detailed information about using DBWO, see
Section 8.11, "Using Data Bus Write Only."
7.2.6.1 Data Bus Grant(DBG)-lnput
The data bus grant (DBG) signal is an input signal (input-only) on the 604. Following are
the state meaning and timing comments for the DBG signal.
State Meaning Asserted-Indicates that the 604 may, with the proper qualification,
assume mastership of the data bus. The 604 derives a qualified data
bus grant when DBG is asserted and DBB, DRTRY, and ARTRY are
negated; that is, the data bus is not busy (DBB is negated), there is
no outstanding attempt to retry the current data tenure (DRTRY is
negated), and there is no outstanding attempt to perform an ARTRY
of the associated address tenure.
Negated-Indicates that the 604 must hold off its data tenures.
Timing Comments Assertion-May occur any time to indicate the 604 is free to take
data bus mastership. It is not sampled until TS or XATS is asserted.
Negation-May occur at any time
to
indicate the 604 cannot assume
data bus mastership.
7 .2.6.2 Data Bus Write Only (DBWO)-lnput
The data bus write only (DBWO) signal is an input signal (input-only) on the 604.
Following are the state meaning and timing comments for the DBWO signal.
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PowerPC 604 RISC Microprocesaor User's Manual