IBM PowerPC 604 User Manual page 130

Ill
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c(
Q)
.s:;
j
Memo~ddress
Memo'b~ddress
Snoop Address
to Data
Cache
=
I!
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1
0
Address Bus
=
I!
"tJ
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a:
Q)
c
j
Copy-Back Address
QO
Copy-Back Address
Share-Invalidate
Queue
Q1
I-line
Fill
AddressQ
0-Une Fill
AddressQO
0-Une
Fill
AddressQ1
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ii:
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6
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0
a:
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0
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a:
N
Q)
i
c
~
0
6
I!
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--- - Co~-Back
Data
(Sword)
---
-
Co~-Back
Data
1 (Sword)
Line
Fill Data
QO (Sword)
Line Fill
Data
Q1 (Sword)
Data In
Register
Write Data
QO (2word)
Write Data
Q1 (2word)
Data Bus
Figure 3-4. Memory Queue Organization
For write operations,
the
address is kept in the memory address queue and the data is kept
in the write buffer until both can
be
sent out in a write transaction. Similarly, for copy-back
operations
the
address is
kept
in
the copy-back address queue and the data is kept
in the
copy-back buffer until both can
be
sent out
in
a burst write transaction. For a cache control
instruction or a store to a shared cache block, the address is kept in the cache control address
queue until an address-only transaction is sent out to broadcast the cache control command.
Because all address queues
in
the 604 are treated as
part
of the coherent memory system,
they are checked against
the
data cache and snoop addresses
to
ensure data consistency and
to maintain MESI coherency protocol.
Chapter 3. Cache and Bus Interface Unit Operation 3-7