Data Valid Window In The Fast-L2/Data Streaming Mode; Interrupt, Checkstop, And Reset Signals; External Interrupts - IBM PowerPC 604 User Manual

To cause data streaming to take place, the system asserts DBG during the last data transfer
of the first data tenure as shown in Figure 8-28. To fully realize the performance gain of
data streaming, the system should be prepared to, but is not required to, supply an
uninterrupted
sequence of TA assertions.
Figure 8-28 shows the operation of the DBG signal when data streaming operations are
taking place on the data bus
0 2
3 4
s
Bus Clock
---TR-A1 TR-A2
TR-A3
6
7 8
TR-83 TR-84
9
I
I
I
------, __
:~~~~~~~~~--Ii
Figure 8·28. Data Transfer In Fast·L2/Data Streaming Mode
8.7.1.3 Data Valid Window in the Fast-L2/Data Streaming Mode
Standard bus mode operations allow data to be transferred no earlier than the cycle before
the ARTRY window that the system defines. In some cases, an asserted AR1RY signal
invalidates the data that was transferred the previous cycle, in the same way DRTRY
cancels data from the previous cycle.
In fast-L2/data streaming mode, the data buffering that allows late cancellation of a data
transfer does not exist, so late cancellation with AR1RY is also impossible. Therefore, the
earliest that data can be transferred in fast-L2/data streaming mode is the first cycle of the
ARTRY window, not the cycle before that.
8.8 Interrupt, Checkstop, and Reset Signals
This section describes external interrupts, checkstop operations, and hard and soft reset
inputs.
8.8.1 External Interrupts
The external interrupt input signals (INT, SMI and MCP) to the 604 eventually force the
processor to take the external interrupt vector, the system management interrupt vector, or
the machine check interrupt if enabled by the MSR[EE] bit (and the HIDO[EMCP] bit in
the case of a machine check interrupt).
8-50
PowarPC 604 RISC Microproceesor User's Manual