Appendix B
Invalid Instruction Forms
This appendix describes how invalid instructions are treated by the PowerPC 604
microprocessor.
B.1 Invalid Forms Excluding Reserved Fields
The following table illustrates the invalid instruction forms of the PowerPC architecture
that are not a result of a nonzero reserved field in the instruction encoding.
Table B-1. Invalid Fonns (Excluding Reserved Flelds)
rA:O
rAln
rAorrB
SPRNot
Mnemonic
80
2
:0
or
rA:O
rA:rT:O
Range
In Range
L:1
Implemented
rA:rD
bcctr
x
bcctrl
x
lbzu
x
lbzux
x
lhzu
x
lhzux
x
lhau
x
lhaux
x
lwzu
x
lwzux
x
stbu
x
stbux
x
sthu
x
sthux
x
stwu
x
stwux
x
lmw
x
x
Appendix B. Invalid Instruction Forms
B-1
-