IBM PowerPC 604 User Manual page 435

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INDEX
FPSCR (floating-point status and control register)
FPSCR instructions, 2-32
FPSCR register description, 2-4
NI bit, 2-18
G
GBL signal, 7-15
GPRO-GPR31 (general-purpose registers), 2-4
Guarded attribute (G bit), 3-10
H
HALTED signal, 7-29
HIDO register
bit settings, 2-10
bits used for cache configuration, 3-15
hardware implementation register, 2-8
HRESET signal, 7-27
VO
tenures, 8-40
IABR (instruction address breakpoint register), 2-8,
2-9
IEEE 1149.1-compliant intelface, 8-52
Illegal instruction class, 2-22
IMMU,5-7
Instruction address breakpoint exception, 4-20
Instruction cache
disabling and enabling, 3-4
organization, 3-4
Instruction dispatch rules, 6-42
Instruction fetch
instruction fetch address generation, 6-8
timing, 6-18
Instruction timing
examples
branch with BTAC hit, 6-25
branch with BTAC miss/decode correction,
6-26
branch with BTAC miss/dispatch correction,
6-28
branch with BTAC miss/execute correction,
6-28
cache hit, 6-19
cache miss, 6-22
instruction flow, 6-17
overview, 1-33, 6-3
tenninology, 6-1
timing considerations, 6-17
lndex-4
Instructions
604-specific, 1-27
64-bit instructions, A-39
branch address calculation, 2-44
branch instructions, A-25
cache management, A-26
classes, 2-21
condition register logical, 2-45, A-25
defined instructions, 2-21
eieio, 2-49
external control instructions, 2-52, A-27
floating-point
arithmetic, 2-30, A-20
compare, 2-32, A-21
FP load instructions, A-24
FP move instructions, A-25
FP rounding and conversion, 2-31
FP status and control register, 2-32
FP store instructions, A-24
FPSCR instructions, A-22
multiply-add, 2-31, A-21
rounding and conversion, A-21
illegal instructions, 2-22
input/output, serialization, 6-35
Instructions, list, A-1, A-10, A-18, A-28, A-39
integer
arithmetic, 2-26, A-18
compare, 2-26, 2-28, A-19
load,A-22
logical, 2-26, 2-28, A-19
rotate, A-20
rotate and shift, 2-29
shift,A-20
store, A-23
isync, 2-49, 4-11
latency summary, 6-45
load and store
address generation, floating-point, 2-40
address generation, integer, 2-35
byte reverse instructions, 2-37, A-23
floating-point move, 2-33
floating-point store, 2-41
handling misalignment, 2-33
integer load, 2-35
integer multiple, 2-38
integer store, 2-36
multiple instructions, A-23
string instructions, 2-39, A-24
memory control instructions, 2-50, 2-54
memory synchronization instructions, 2-47
mtcrf, 2-46, 6-44
optional instructions, A-39
processor control instructions, 2-46, 2-48, 2-52,
A-26
PowerPC 604 RISC Microprocessor User's Manual