Rename Register Operation; Instruction Execution Timing - IBM PowerPC 604 User Manual

6.4.6.1 Rename Register Operation
To avoid contention for a given register file location in the course of out-of-order execution,
the 604 provides rename registers for the storage of instruction results prior
to
their
commitment (in program order)
to
the architecturally defined register by the completion
unit. Register renaming minimizes architectural resource dependencies, namely the output
and antidependencies, that would otherwise limit opportunities for out-of-order execution.
Twelve rename registers are provided for the GPRs, eight for the FPRs, and eight for the
condition register.
A GPR rename buffer entry is allocated when an instruction that modifies a GPR is
dispatched. This entry is marked as allocated but not valid. When
the
instruction executes,
it writes its result
to
the entry and sets the valid bit. When
the
instruction completes, its
result is copied from
the
rename buffer entry
to
the GPR and the entry is freed for
reallocation. For load with update instructions that modify two GPRs, one for load data and
another for address, two rename buffer entries are allocated.
The rename register for the GPRs is shown in Figure 6-13.
Chapter
e.
Instruction Timing 6-31