Direct-Store Operation - IBM PowerPC 604 User Manual

8.6 Direct-Store Operation
The 604 defines separate memory-mapped and 1/0 address spaces, or segments,
distinguished by the corresponding segment register T bit in the address translation logic
of the 604. If the T bit is cleared, the memory reference is a normal memory-mapped access
and can use the virtual memory management hardware of the 604. If the T bit is set, the
memory reference is a direct-store access.
The following points should be considered for direct-store accesses:
• The use of direct-store segment (referred to as direct-store segments in the
architecture specification) accesses may have a significant impact on the
performance of the 604. The provision of direct-store segment access capability by
the 604 is to provide compatibility with earlier hardware 1/0 controllers and may not
be provided in future derivatives of the 604 family.
• Direct-store accesses must be strongly ordered; for example, these accesses must
run on the bus strictly in order with respect to the instruction stream.
• Direct-store accesses must provide synchronous error reporting. Chapter 3, "Cache
and Bus Interface Unit Operation," describes architectural aspects of direct-store
segments, as well as an overview of the segmented address space management of
PowerPC processors.
The 604 has a single bus interface to support both memory accesses and direct-store
segment accesses.
The direct-store protocol for the 604 allows for the transfer of 1 to 128 bytes of data
between the 604 and the bus unit controller (BUC) for each single load or store request
issued by the program. The block of data is transferred by the 604 as multiple single-beat
bus transactions (individual address and data tenure for each transaction) until completion.
The program waits for the sequence of bus transactions to be completed so that a final
completion status (error or no error) can be reported precisely with respect to the program
flow. The completion status is snooped by the 604 from a bus transaction run by the BUC.
The system recognizes the assertion of the TS signal as the start of a memory-mapped
access. The assertion of XATS indicates a direct-store access. This allows memory-mapped
devices to ignore direct-store transactions. If XATS is asserted, the access is to a direct-
store space and the following extensions to the memory access protocol apply:
• A new set of bus operations are defined. The transfer type, transfer burst, and
transfer size signals are redefined for direct-store operations; they convey the
opcode for the 1/0 transaction (see Table 8-8).
• There are two beats of address for each direct-store transfer. The first beat (packet
0) provides basic address information such as the segment register and the sender
tag and several control bits; the second beat (packet 1) provides additional
addressing bits from the segment register and the logical address.
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PowerPC 604 RISC Microprocesaor Ueer's Manual