Power Management - IBM PowerPC 604 User Manual

Like the external interrupt, a system management interrupt is signaled to the 604 by the
assertion of an input signal. The system management interrupt signal (SMI) is expected
to
remain asserted until the interrupt is taken. If the SMI signal is negated early, recognition
of the interrupt request is not guaranteed. After the 604 begins execution of the system
management interrupt handler, the system can safely negate the SMI signal. After the SMI
signal is detected, the 604 stops dispatching instructions and waits for all pending
instructions to complete. This allows any instructions in progress that need to take an
exception to do so before the system management interrupt is taken.
When the exception is taken, 604 vectors to the system management interrupt vector in the
interrupt table. The vector offset of the system management is Ox01400.
4.5.16 Power Management
Nap mode is a simple power-saving mode, in which all internal processing and bus
operation is suspended. Software initiates nap mode by setting MSR[POW]. After this bit
is set, the 604 suspends instruction dispatch and waits for all activity, including active and
pending bus transactions, to complete. It then shuts down the internal chip clocks and enters
nap mode state. The 604 indicates the internal idle state by asserting the HALTED output
regardless whether the clock is stopped.
Nap mode must be entered by using the following code sequence:
naploop:
sync
mtmsr <GPR> (modify the POW bit
.QD.JJl;
at this point the EE bit should
have already been enabled by the software)
isync
ba naploop
Since this code sequence creates an infinite loop, the programmer should ensure that the
exit routine (one of the exception handler routines listed below) properly updates SRRO to
return to a point outside of this loop.
While the 604 is in nap mode, all internal activity except for decrementer, timebase, and
interrupt logic is stopped. During nap mode, the 604 does not snoop; if snooping is
required, the system may assert the RUN signal. The clocks run while the RUN signal is
asserted, but instruction execution does not resume. The HALTED output is deasserted
to
indicate any bus activity, including a cache block pushout caused by a snoop request, and
is reasserted to indicate that the processor is idle and that the RUN signal can be safely
deasserted to stop the clocks. The maximum latency from the RUN signal assertion to the
starting of clock is three bus clock cycles.
To ensure proper handling of snoops in a multiprocessor system when a processor is the
first to enter nap mode, the system must assert the RUN signal no later than the assertion
of BG to another bus master. This constraint is necessary to ensure proper handling of
snoops when the first processor is entering nap mode.
Chapter 4. Exceptions
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