Table of Contents
Advertisement
5.1.4 Memory Protection Facilities
In addition to the translation of effective addresses to physical addresses, the MMUs
provide access protection of supervisor areas from user access and can designate areas of
memory as read-only as well as no-execute or guarded. Table 5-2 shows the protection
options supported by the MMUs for pages.
Table S-2. Access Protection Options for Pages
User Read
User
Supervisor Read
Supervisor
Option
I-Fetch
Data
Write
I-Fetch
Data
Write
Si.pervisor-only
-
-
-
" "
"
Si.pervisor-only·nCH1xecute
-
-
-
-
"
"
Si.pervisor-wrile-only
"
"
-
"
"
"
Si.pervisor-wrile-only-nCH1xecute
-
"
-
-
"
"
Both user/supervisor
"
"
"
"
"
"
Both user-/si.pervlsor-nCH1xecute
-
"
"
-
"
"
Both read-only
" "
-
" "
-
Both read-only-no-execute
-
"
-
-
"
-
Guarded
-./ Access permitted
- Protection violation
The operating system determines whether instruction can be fetched from an area of
memory for which the no-execute option is provided in the segment descriptor. Each of the
remaining options is enforced based on a combination of information in the segment
descriptor and the page table entry. Thus, the supervisor-only option allows only read and
write
operations generated while the processor is operating in supervisor mode
(corresponding to MSR[PR]
=
0)
to
access the page. User accesses that map into a
supervisor-only page cause an exception to be taken.
Finally, there is a facility in the VEA and OEA that allows pages or blocks to be designated
as guarded preventing out-of order accesses that may cause undesired side effects. For
example, areas of the memory map that are used to control
1/0
devices can be marked as
guarded so that accesses (for example, instruction prefetches) do not occur unless they are
explicitly required by the program.
For more information on memory protection, see "Memory Protection Facilities," in
Chapter 7, "Memory Management," in the
The Programming Environments Manual.
Chapter 5. Memory Management
5-11
Advertisement
Chapters
Table of Contents
