Real Addressing Mode; Block Address Translation; Memory Segment Model - IBM PowerPC 604 User Manual

Execution of this instruction causes all entries in the congruence class corresponding to the
presented EA to be invalidated in the processor executing the instruction and in the other
processors attached to the same bus.
The tlbsync operation appears on the bus as a distinct operation, that causes
synchronization of snooped tlbie instructions. Section 5.4.3.2, "TLB Invalidation,"
describes the TLB invalidation mechanisms in the 604.
5.2 Real Addressing Mode
If address translation is disabled (MSR[IR]
=
0 or MSR[DR]
=
0) for a particular access,
the effective address is treated as the physical address and is passed directly to the memory
subsystem as described in Chapter 7, "Memory Management," in
The Programming
Environments Manual.
For information on the synchronization requirements for changes to MSR[IR] and
MSR[DR], refer to Section 2.3.2.4, "Synchronization."
5.3 Block Address Translation
The block address translation (BAT) mechanism in the OEA provides a way to map ranges
of effective addresses larger than a single page into contiguous areas of physical memory.
Such areas can be used for data that is not subject to normal virtual memory handling
(paging), such as a memory-mapped display buffer or an extremely large array of numerical
data.
Block address translation in the 604 is described in Chapter 7, "Memory Management," in
The Programming Environments Manual
for 32-bit implementations.
5.4 Memory Segment Model
The 604 adheres to the memory segment model as defined in Chapter 7, "Memory
Management," in
The Programming Environments Manual
for 32-bit implementations.
Memory in the PowerPC OEA is divided into 256-Mbyte segments. This segmented
memory model provides a way to map 4-Kbyte pages of effective addresses to 4-Kbyte
pages in physical memory (page address translation), while providing the programming
flexibility afforded by a large virtual address space (52 bits).
The segment/page address translation mechanism may
be
superseded by the block address
translation (BAT) mechanism described in Section 5.3, "Block Address Translation." If
not, the translation proceeds in the following two steps:
1. from effective address to the virtual address (which never exists as a specific entity
but can be considered to be the concatenation of the virtual page number and the
byte offset within a page), and
2. from virtual address to physical address.
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PowerPC 604 RISC Microprocessor User's Manual