Powerpc 604 Microprocessor Hardware Implementation - IBM PowerPC 604 User Manual

1.2 PowerPC 604 Microprocessor Hardware
Implementation
This section provides an overview of the 604's hardware implementation, including
descriptions of the functional units, shown in Figure 1-2, the cache implementation, MMU,
and the system interface.
Note that Figure 1-2 provides a more detailed block diagram than that presented in
Figure 1-1-showing the additional data
paths
that contribute to the improved efficiency in
instruction execution and more clearly indicating the relationships between execution units
and their associated register files.
Branch
Corraction
Fetch Unit
Dispatch Unit
(Four-instruction
dispatch)
Instruction Dispatch Buses
GPA Operand Buses
r - -
r. - -
r - - ,•- - - - -.- - -
l
I GPA Result Buses I I
1
1
-~..__...,.
_ _ ...., _ _ _
to-iol-
I FPA Operand Buses
I
f
I-
,---1.---l
I I FPA Result Buses I I
I I
Instruction 16-Kbyte data cache
Completion Unit 4-way, 8 words/block
Figure
1-2.
Block Diagram-Internal Data Paths
Chapter 1. Overview
AesultBuses
Operand Buses
Dispatch Buses
I
12.
a..
u..
C\I
Cl)
1-7