Timing Example-Branch With Btac Miss/Decode Correction - IBM PowerPC 604 User Manual

The timing for this example is described, cycle-by-cycle, as follows:
0. In clock cycle 0, instructions 0--3 are fetched. The target instruction of the be
instruction is found in the BTAC.
1.
In cycle 1, instructions 0--3 are decoded and instructions 4-7, using the address in
the BTAC, are fetched.
2. In cycle 2, instructions 0--3 are dispatched and instructions 4-7 are decoded
3. In cycle 3, instructions 0--3 are in the execute stage and instructions 4-7 are in the
dispatch stage.
4. In cycle 4, instructions 0, 2, and 3 are in the complete stage, but only instruction 0
is allowed to complete and write back because the Id instruction ( 1) is still in the
execute stage of the LSU pipeline. Instructions 2and 3 wait in the complete stage.
Instructions 4-7 all enter the execute stage.
5.
In cycle
5,
the Id (1) instruction is able to complete and write back, allowing the add
instruction to write back and vacate the pipeline in the next cycle. The br instruction
also completes. Because the branch is taken, the or.(4) instruction, which could
otherwise write back in this cycle, stays in the complete stage and completes and
writes back in the next cycle. The emp ( 5) instruction also enters the complete stage;
Id (6) and mulli (7) enter the second stages of the LSU and MCIU pipelines,
respectively.
6. In cycle 6, instructions 4-6 complete and write back their results. The mulli
instruction, which is one of the instructions that can complete and write back during
its final cycle in the execute stage, occupies the execute and complete stages, but
cannot write back because both GPR write-back
ports
are occupied by the or and Id
instructions.
7. The mulli instruction writes back its results.
6.4.4.1.2 Timing Example-Branch with BTAC Miss/Decode Correction
In the example shown in Figure 6-10, the branch target address is not found in the BTAC
during the fetch cycle of the be instruction, as was the case in Figure 6-9. This one-cycle
delay causes the second group of instructions to be executed one cycle later than if there is
aBTAC hit.
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PowerPC 604 RISC Microprocessor User's Manual