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3.8.6 Data Cache Block Flush (dcbf)
As
defined in the VEA, when a Data Cache Block Flush (debt) instruction is executed, the
effective address is computed, translated, and checked for protection violations.
If
the 604
does not have modified data in this cache block, it broadcasts a flush operation onto the 604
bus. If the addressed cache block is in the cache, the 604 marks this data as invalid.
However, if the cache block is present and modified, the processor pushes the modified data
into the memory queue for arbitration onto the 604 bus and the cache block is marked as
invalid.
3.8.7 Data Cache Block Invalidate (dcbi)
As
defined in the OEA, when a Data Cache Block Invalidate ( dcbi) instruction is executed,
the effective address is computed, translated, and checked for protection violations.
The 604 broadcasts a kill operation onto the 604 bus. If the addressed cache block is in the
cache, the 604 marks this data as invalid regardless of whether the data is modified.
Because this instruction may effectively destroy modified data, it is privileged and has store
semantics with respect to protection; that is, write pennission is required for the DCBI (kill)
operation.
3.9 Basic Cache Operations
This section describes operations that can occur to the cache, and how these operations are
implemented in the 604.
3.9.1 Cache Reloads
A cache block is reloaded after a read miss occurs in the cache. The cache block that
contains the address is updated by a burst transfer of the data from system memory. Note
that if a read miss occurs in a multiprocessor system, and the data is modified in another
cache, the modified data is first written to external memory before the cache reload occurs.
3.9.2 Cache Cast-Out Operation
The 604 uses an LRU replacement algorithm to determine which of the four possible cache
locations should
be
used for a cache update. Updating a cache block causes any modified
data associated with the least-recently used element to be written back, or cast out, to
system memory.
3.9.3 Cache Block Push Operation
When a cache block in the 604 is snooped and hit by another processor and the data is
modified, the cache block must be written to memory and made available to the snooping
device. The cache block that is hit is said to
be
pushed out onto the bus. The 604 supports
two kinds of push operations-normal push operations and enveloped high-priority push
operations, which are described in Section 3.9.7, "Enveloped High-Priority Cache Block
Push Operation."
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PowerPC 604 RISC Microprocessor User's Manual
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