Address Bus (Ao-A31}-0Utput (Direct-Store Operations); Address Bus (Ao-A31)-Lnput (Direct-Store Operations); Address Bus Parity (Apo-Ap3); Address Bus Parity (Apo-Ap3)-0Utput - IBM PowerPC 604 User Manual

7.2.3.1.3 Address Bus (AO-A31)-0utput (Direct-Store Operations)
Following are the state meaning and timing comments for the address bus signals (AO to
A31) for output direct-store operations on the 604.
State Meaning Asserted/Negated-For direct-store operations where the 604 is the
master, the address tenure consists of two packets (each requiring a
bus cycle). For packet 0, these signals convey control and tag
information. For packet 1, these signals represent the physical
address of the data to be transferred. For reply operations, the
address bus contains control, status, and tag information.
Timing Comments Assertion/Negation-Address tenure consists of two beats. The first
beat occurs on the bus clock cycle after a qualified bus grant,
coinciding with XATS. The address bus transitions to the second
beat on the next bus clock cycle.
High Impedance-Occurs on the bus clock cycle after AACK is
asserted
7.2.3.1.4 Address Bus (AO-A31)-lnput (Direct-Store Operations)
Following are the state meaning and timing comments for input direct-store operations on
the 604.
State Meaning Asserted/Negated-When the 604 is not the master, it snoops (and
checks address parity) on the first address beat only of all direct-store
operations for an 1/0 reply operation with a receiver tag that matches
its PID tag. See Section 8.6, "Direct-Store Operation."
Timing Comments Assertion/Negation-The first beat of the
J/O
transfer address tenure
coincides with XATS, with the second address bus beat on the
following cycle.
7 .2.3.2 Address Bus Parity (APO-AP3)
The address bus parity (APO-AP3) signals are both input and output signals reflecting one
bit of odd-byte parity for each of the four bytes of address when a valid address is on the
bus.
7.2.3.2.1 Address Bus Parity (APO-AP3)-0utput
Following are the state meaning and timing comments for the APO-AP3 output signal on
the 604.
State Meaning
7·8
Asserted/Negated-Represents odd parity for each of four bytes of
the physical address for a transaction. Odd parity means that an odd
number of bits, including the parity bit, are driven
high.
The signal
assignments correspond to the following:
APO AO-A7
APl A8-A15
AP2 A16-A23
AP3 A24-A31
PowerPC 604 RISC Microproceesor User's Manual