Instructions Not Supported In Direct-Store Segments; Instructions With No Effect In Direct-Store Segments; Direct-Store Segment Translation Summary Flow - IBM PowerPC 604 User Manual

5.5.3 Instructions Not Supported in Direct-Store Segments
The following instructions are not supported at all and cause a DSI exception (with
DSISR[5] set) when issued with an effective address that selects a segment descriptor that
has T
=
1 (or when MSR[DR]
=
0):
• lwarx
• stwcx.
• eciwx
• ecowx
5.5.4 Instructions with No Effect In Direct-Store Segments
The following instructions are executed as no-ops when issued with an effective address
that selects a segment where T
=
1:
• debt
• dcbtst
• dcbf
• dcbi
• dcbst
• dcbz
• icbi
5.5.5 Direct-Store Segment Translation Summary Flow
Figure 5-11 shows the flow used by the MMU when direct-store segment address
translation is selected This figure expands the direct-store segment translation stub found
in Figure 5-6 for both instruction and data accesses. In the case of a floating-point load or
store operation to a direct-store segment, other implementations may not take an alignment
exception, as is allowed by the PowerPC architecture. In the case of an eciwx, ecowx,
lwarx, or stwcx. instruction, the implementation either sets the DSISR register as shown
and causes the DSI exception, or causes boundedly undefined results.
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