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IBM PowerPC 604 User Manual
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Contents
Table of Contents
Bookmarks
Table of Contents
Table of Contents
Paragraph
About this Book
Audience
Organization
Suggested Reading
Conventions
Acronyms and Abbreviations
Overview
Powerpc 604 Microprocessor Features
Powerpc 604 Microprocessor Hardware Implementation
Instruction Flow
Fetch Unit
Decode/Dispatch Unit
Branch Processing Unit (BPU)
Completion Unit
Rename Buffers
Execution Units
Integer Units (Ius)
Floating-Point Unit (FPU)
Load/Store Unit (LSU)
Memory Management Units (Mmus)
Cache Implementation
Instruction Cache
Data Cache
System Interface/Bus Interface Unit (BIU)
Memory Accesses
Signals
Signal Coofiguration
Clocking
Powerpc 604 Microprocessor Execution Model
Levels of the Powerpc Architecture
Registers and Programming Model
General-Purpose Registers (Gprs)
Floating-Point Registers (Fprs)
Condition Register (CR)
Floating-Point Status and Control Register (FPSCR)
Machine State Register (MSR)
Segment Registers (Srs)
Special-Purpose Registers (Sprs)
User-Level Sprs
Supervisor-Level Sprs
Instruction Set and Addressing Modes
Powerpc Instruction Set and Addressing Modles
Instruction Set
Calculating Effective Addresses
Exception Model
Instruction Timing
Power Management-Nap Mode
Performance Monitor
Powerpc 604 Processor Programming Model
The Powerpc 604 Processor Register Set
Register Set
604-Specific Registers
Instruction Address Breakpoint Register (IABR)
Processor Identification Register (PIR)
Hardware Implementation-Dependent Register 0
Performance Monitor Registers
Monitor Mode Control Register 0 (MMCRO)
Performance Monitor Counter Registers (Pmcl and PMC2)
Sampled Instruction Address Register (SIA)
Sampled Data Address Register (SDA)
Operand Conventions
Floating-Point Execution Models-UISA
Da~ Organization in Memory and Data Transfers
Alignment and Misaligned Accesses
Floating-Point Operand
Effect of Operand Placement on Performance
Instruction Set Summary
Classes of Instructions
Definition of Boundedly Undefined
Defined Instruction Class
Illegal Instruction Class
Reserved Instruction Class
Addressing Modes
Memory Addressing
Memory Operands
Effective Address Calculation
Synchronization
Context Synchronization
Execution Synchronization
Instruction-Related Exceptions
Instruction Set Overview
Powerpc UISA Instructions
Integer Instructions
Integer Arithmetic Instructions
Integer Compare Instructions
Integer Logical Instructions
Integer Rotate and Shift Instructions
Floating-Point Instructions
Floating-Point Arithmetic Instructions
Floating-Point Multiply-Add Instructions
Floating-Point Rounding and Conversion Instructions
Floating-Point Compare Instructions
Floating-Point Status and Control Register Instructions
Floating-Point Move Instructions
Load and Store Instructions
Self-Modifying Code
Integer Load and Store Address Generation
Register Indirect Integer Load Instructions
Integer Store Instructions
Integer Load and Store with Byte Reverse Instructions
Integer Load and Store Multiple Instructions
Integer Load and Store String Instructions
Floating-Point Load and Store Address Generation
Floating-Point Store Instructions
Branch and Flow Control Instructions
Branch Instruction Address Calculation
Branch Instructions
Condition Register Logical Instructions
Trap Instructions
Move To/From Condition Register Instructions
System Linkage Lnstruction-UISA
Move To/From Special-Purpose Register Instructions (UISA)
Memory Synchronization Lnstructions-UISA
Powerpc VEA Instructions
Processor Control Instructions-VEA
Move from Time Base Instruction
Memory Synchronization Instructions-VEA
Memory Control Instructions-VEA
User-Level Cache Instructions-VEA
User-Level Cache Instructions
Optional External Control Instructions
Powerpc OEA Instructions
External Control Instructions
System Linkage Instructions-CEA
Memory Control Instructions-DEA
Supervisor-Level Cache Management Instruction-(OEA)
Segment Register Manipulation Instructions
Translation Lookaside Buffer Management Instruction
Segment Register Manipulation Instructions (OEA)
Translation Lookaside Buffer Management Lnstructions-(OEA)
Recommended Simplified Mnemonics
Cache and Bus Interface Unit Operation
Data Cache Organization
Instruction Cache Organization
Mmus/Bus Interface Unit
Memory Coherency Actions
604-Initiated Load and Store Operations
Memory Coherency Actions on Load Operations
Sequential Consistency
Sequential Consistency Within a Single Processor
Weak Consistency between Multiple Processors
Memory Coherency Actions on Store Operations
Sequential Consistency Within Multiprocessor Systems
Memory and Cache Coherency
Data Cache Coherency Protocol
MESI State Definitions
Coherency and Secondary Caches
Page Table Control Bits
MESI State Diagram
Coherency Paradoxes in Single-Processor Systems
Coherency Paradoxes in Multiple-Processor Systems
Cacheconfiguration
Cache Control Instructions
Instruction Cache Block Invalidate (Icbi)
Instruction Synchronize (Isync)
Data Cache Block Touch (Debt) and Data Cache Block Touch for Store (Dcbtst)
Data Cache Block Set to Zero (Dcbz)
Data Cache Block Store (Dcbst)
Data Cache Block Flush (Dcbf)
Data Cache Block Invalidate (Dcbi)
Basic Cache Operations
Cache Reloads
Cache Cast-Out Operation
Cache Block Push Operation
Atomic Memory References
Snoop Response to Bus Operations
Cache Reaction to Specific Bus Operations
Enveloped High-Priority Cache Block Push Operation
Bus Operations Caused by Cache Control Instructions
Cache Control Instructions
Cache Actions
Cache Actions
Access to Direct-Store Segments
Exceptions
Powerpc 604 Microprocessor Exceptions
Exception Recognition and Priorities
Exception Processing
MSR Bit Settings
Enabling and Disabling Exceptions
Steps for Exception Processing
Setting MSR[RI]
Returning from an Exception Handler
Process Switching
Exception Definitions
MSR Setting Due to Exception
Machine Check Exception (Ox00200)
System Reset Exception-Register Settings
Machine Check Exception Enabled (MSR[ME] 1)
Checkstop State (MSR[ME] 0)
Isi Exception (Ox00400)
External Interrupt Exception (Ox00500)
Alignment Exception (Ox00600)
Program Exception (Ox00700)
Floating-Point Unavailable Exception (Ox00800)
Decrementer Exception (Ox00900)
System Call Exception (Oxoocoo)
Trace Exception (Oxood00)
Floating-Point Assist Exception (Oxooeoo)
Instruction Address Breakpoint Exception (Ox01300)
System Management Interrupt (Ox01400)
Power Management
Memory Management
MMU Overview
Memory Addressing
MMU Organization
Address Translation Mechanisms
Memory Protection Facilities
Access Protection Options for
General Flow of MMU Address Translation
Real Addressing Mode and Block Address Translation Selection
Page and Direct-Store Interface Address Translation Selection
Selection of Page Address Translation
Selection of Direct-Store Interface Address Translation
MMU Exceptions Summary
MMU Instructions and Register Summary
TLB Entry Invalidation
Powerpc 604 Microprocessor Instruction Summary-Control Mmus
Powerpc 604 Microprocessor MMU Registers
Real Addressing Mode
Block Address Translation
Memory Segment Model
Page History Recording
Referenced Bit
Changed Bit
Scenarios for Referenced and Changed Bit Recording
Page Memory Protection
TLB Description
TLB Organization
TLB Invalidation
Page Address Translation Summary
Page Table Search Operation
Page Table Updates
Segment Register Updates
Direct-Store Interface Address Translation
Direct-Store Interface Accesses
Direct-Store Segment Protection
Instructions Not Supported in Direct-Store Segments
Instructions with no Effect in Direct-Store Segments
Direct-Store Segment Translation Summary Flow
Instruction Timing
Instruction Timing Overview
Pipeline Structures
Description of Pipeline Stages
Fetch Stage
Decode Stage
Dispatch Stage
Execute Stage
Complete Stage
Write-Back Stage
MMU Overview
Cache Overview
Bus Interface Overview
Memory Operations
Write-Back Mode
Write-Through Mode
Cache-Inhibited Mode
Timing Considerations
General Instruction Flow
Instruction Fetch Timing
Cache Miss Timing Example
Cache Arbitration
Branch Prediction
Branch Timing Examples
Timing Example-Branch Timing for a BTAC Hit
Timing Example-Branch with BTAC Miss/Decode Correction
Timing Example-Branch with BTAC Miss/Dispatch Correction
Timing Example-Branch with BTAC Miss/Execute Correction
Speculative Execution
Instruction Dispatch and Completion Considerations
Rename Register Operation
Instruction Execution Timing
Execution Unit Considerations
Instruction Serialization
Dispatch Serialization Mode
Execution Serialization Mode
Postdispatch Serialization Mode
Serialization of String/Multiple Instructions
Serialization of Input/Output
Execution Unit Timings
Branch Unit Instruction Timings
Integer Unit Instruction Timings
Floating-Point Unit Instruction Timings
Load/Store Unit Instruction Timings
Isync, Rfi, and Sc Instruction Timings
Instruction Scheduling Guidelines
Instruction Dispatch Rules
Additional Programming Tips for the Powerpc 604 Processor
Instruction Latency Summary
Signal Descriptions
Signal Configuration
Signal Descriptions
Address Bus Arbitration Signals
Bus Request (BR)-Output
Address Bus Busy (ABB)
Address Bus Busy (ABB)-Output
Address Transfer Start Signals
Transfer Start (TS)
Transfer Start {TS)-Output
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