Integer Load And Store With Byte Reverse Instructions - IBM PowerPC 604 User Manual

Table 2-21. Integer Store Instructions
Name Mnemonic
Operand Syntax
Store Byte stb
rS,d(rA)
Store Byte Indexed stbx
rS,rA,rB
Store Byte with Update
stbu
rS,d(rA)
Store Byte with Update Indexed stbux rS,rA,rB
Store Half Word sth rS,d(rA)
Store Haff Word Indexed
sthx
rS,rA,rB
Store Haff Word with Update sthu rS,d(rA)
Store Haff Word with Update Indexed sthux
rS,rA,rB
Store Word
stw rS,d(rA)
Store Word Indexed stwx rS,rA,rB
Store Word with Update stwu rS,d(rA)
Store Word with Update Indexed stwux rS,rA,rB
Implementation Notes-The following notes describe the 604 implementation of integer
store instructions:
• In the PowerPC architecture, the Re bit must be zero for almost all load and store
instructions. If the Re bit is one, the instruction form is invalid. These include the
integer store indexed instructions (stbx, stbux, sthx, sthux, stwx, stwux). In the
604, executing one of these invalid instruction forms causes CRO to be set
to
an
undefined value.
• For the store with update instructions (stbu, stbux, sthu, sthux, stwu, stwux, stfsu,
stfsux, stfdu, stfdux), when r A= 0, the instruction form is considered invalid. In
this case, the 604 sets GPRO to an undefined value.
2.3.4.3.5 Integer Load and Store with Byte Reverse Instructions
Table 2-22 describes integer load and store with byte reverse instructions. When used in a
PowerPC system operating with the default big-endian byte order, these instructions have
the effect of loading and storing data in little-endian order. Likewise, when used in a
PowerPC system operating with little-endian byte order, these instructions have the effect
of loading and storing data in big-endian order. For more information about big-endian and
little-endian byte ordering, see Section 3.2.2, "Byte Ordering," in The Programming
Environments Manual.
Implementation Note-In the PowerPC architecture, the Re bit must be zero for almost
all load and store instructions. If the Re bit is one, the instruction form is invalid. These
include the load and store with byte-reversal instructions (lhbrx, lwbrx, sthbrx, stwbrx).
Chapter 2. PowerPC 604 Processor Programming Model
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